include/configs/Sandpoint8245.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /* ------------------------------------------------------------------------- */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MPC824X          1
  23 #define CONFIG_MPC8245          1
  24 #define CONFIG_SANDPOINT        1
  25
  26 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  27 #define CONFIG_SYS_LDSCRIPT     "board/sandpoint/u-boot.lds"
  28
  29 #if 0
  30 #define USE_DINK32              1
  31 #else
  32 #undef USE_DINK32
  33 #endif
  34
  35 #define CONFIG_CONS_INDEX     3               /* set to '3' for on-chip DUART */
  36 #define CONFIG_BAUDRATE         9600
  37 #define CONFIG_DRAM_SPEED       100             /* MHz                          */
  38
  39 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  40
  41
  42 /*
  43  * BOOTP options
  44  */
  45 #define CONFIG_BOOTP_BOOTFILESIZE
  46 #define CONFIG_BOOTP_BOOTPATH
  47 #define CONFIG_BOOTP_GATEWAY
  48 #define CONFIG_BOOTP_HOSTNAME
  49
  50
  51 /*
  52  * Command line configuration.
  53  */
  54 #include <config_cmd_default.h>
  55
  56 #define CONFIG_CMD_DHCP
  57 #define CONFIG_CMD_ELF
  58 #define CONFIG_CMD_I2C
  59 #define CONFIG_CMD_EEPROM
  60 #define CONFIG_CMD_NFS
  61 #define CONFIG_CMD_PCI
  62 #define CONFIG_CMD_SNTP
  63
  64
  65 /*
  66  * Miscellaneous configurable options
  67  */
  68 #define CONFIG_SYS_LONGHELP             1               /* undef to save memory         */
  69 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt       */
  70 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  71 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size    */
  72 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
  73 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  74 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address         */
  75 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
  76
  77 /*-----------------------------------------------------------------------
  78  * PCI stuff
  79  *-----------------------------------------------------------------------
  80  */
  81 #define CONFIG_PCI                              /* include pci support          */
  82 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  83 #undef CONFIG_PCI_PNP
  84
  85
  86 #define CONFIG_EEPRO100
  87 #define CONFIG_SYS_RX_ETH_BUFFER        8               /* use 8 rx buffer on eepro100  */
  88 #define CONFIG_NATSEMI
  89 #define CONFIG_NS8382X
  90
  91 #define PCI_ENET0_IOADDR        0x80000000
  92 #define PCI_ENET0_MEMADDR       0x80000000
  93 #define PCI_ENET1_IOADDR        0x81000000
  94 #define PCI_ENET1_MEMADDR       0x81000000
  95
  96
  97 /*-----------------------------------------------------------------------
  98  * Start addresses for the final memory configuration
  99  * (Set up by the startup code)
 100  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 101  */
 102 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 103 #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
 104
 105 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 106
 107 #if defined (USE_DINK32)
 108 #define CONFIG_SYS_MONITOR_LEN          0x00030000
 109 #define CONFIG_SYS_MONITOR_BASE 0x00090000
 110 #define CONFIG_SYS_RAMBOOT              1
 111 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 112 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 113 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 114 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 115 #else
 116 #undef  CONFIG_SYS_RAMBOOT
 117 #define CONFIG_SYS_MONITOR_LEN          0x00030000
 118 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 119
 120
 121 #define CONFIG_SYS_INIT_RAM_ADDR     0x40000000
 122 #define CONFIG_SYS_INIT_RAM_SIZE      0x1000
 123 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 124
 125 #endif
 126
 127 #define CONFIG_SYS_FLASH_BASE           0xFFF00000
 128 #if 0
 129 #define CONFIG_SYS_FLASH_SIZE           (512 * 1024)    /* sandpoint has tiny eeprom    */
 130 #else
 131 #define CONFIG_SYS_FLASH_SIZE           (1024 * 1024)   /* Unity has onboard 1MByte flash */
 132 #endif
 133 #define CONFIG_ENV_IS_IN_FLASH  1
 134 #define CONFIG_ENV_OFFSET               0x00004000      /* Offset of Environment Sector */
 135 #define CONFIG_ENV_SIZE         0x00002000      /* Total Size of Environment Sector */
 136
 137 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 512 kB for malloc()  */
 138
 139 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on             */
 140 #define CONFIG_SYS_MEMTEST_END          0x04000000      /* 0 ... 32 MB in DRAM          */
 141
 142 #define CONFIG_SYS_EUMB_ADDR            0xFC000000
 143
 144 #define CONFIG_SYS_ISA_MEM              0xFD000000
 145 #define CONFIG_SYS_ISA_IO               0xFE000000
 146
 147 #define CONFIG_SYS_FLASH_RANGE_BASE     0xFF000000      /* flash memory address range   */
 148 #define CONFIG_SYS_FLASH_RANGE_SIZE     0x01000000
 149 #define FLASH_BASE0_PRELIM      0xFFF00000      /* sandpoint flash              */
 150 #define FLASH_BASE1_PRELIM      0xFF000000      /* PMC onboard flash            */
 151
 152 /*
 153  * select i2c support configuration
 154  *
 155  * Supported configurations are {none, software, hardware} drivers.
 156  * If the software driver is chosen, there are some additional
 157  * configuration items that the driver uses to drive the port pins.
 158  */
 159 #define CONFIG_HARD_I2C         1               /* To enable I2C support */
 160 #undef  CONFIG_SYS_I2C_SOFT
 161 #define CONFIG_SYS_I2C_SPEED    400000
 162 #define CONFIG_SYS_I2C_SLAVE    0x7F
 163
 164 #ifdef CONFIG_SYS_I2C_SOFT
 165 #error "Soft I2C is not configured properly.  Please review!"
 166 #define CONFIG_SYS_I2C
 167 #define CONFIG_SYS_I2C_SOFT_SPEED       50000
 168 #define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 169 #define I2C_PORT                3               /* Port A=0, B=1, C=2, D=3 */
 170 #define I2C_ACTIVE              (iop->pdir |=  0x00010000)
 171 #define I2C_TRISTATE            (iop->pdir &= ~0x00010000)
 172 #define I2C_READ                ((iop->pdat & 0x00010000) != 0)
 173 #define I2C_SDA(bit)            if(bit) iop->pdat |=  0x00010000; \
 174                                 else    iop->pdat &= ~0x00010000
 175 #define I2C_SCL(bit)            if(bit) iop->pdat |=  0x00020000; \
 176                                 else    iop->pdat &= ~0x00020000
 177 #define I2C_DELAY               udelay(5)       /* 1/4 I2C clock duration */
 178 #endif /* CONFIG_SYS_I2C_SOFT */
 179
 180 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57            /* EEPROM IS24C02               */
 181 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1               /* Bytes of address             */
 182 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 183 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 184
 185 #define CONFIG_SYS_FLASH_BANKS          { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
 186
 187 /*-----------------------------------------------------------------------
 188  * Definitions for initial stack pointer and data area (in DPRAM)
 189  */
 190
 191
 192 /* #define CONFIG_WINBOND_83C553        1       / *has a winbond bridge                 */
 193 #define CONFIG_SYS_USE_WINBOND_IDE      0       /*use winbond 83c553 internal IDE ctrlr */
 194 #define CONFIG_SYS_WINBOND_ISA_CFG_ADDR    0x80005800   /*pci-isa bridge config addr    */
 195 #define CONFIG_SYS_WINBOND_IDE_CFG_ADDR    0x80005900   /*ide config addr               */
 196
 197 #define CONFIG_SYS_IDE_MAXBUS           2   /* max. 2 IDE busses        */
 198 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 199
 200 /*
 201  * NS87308 Configuration
 202  */
 203 #define CONFIG_NS87308                  /* Nat Semi super-io controller on ISA bus */
 204
 205 #define CONFIG_SYS_NS87308_BADDR_10     1
 206
 207 #define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1   | \
 208                                   CONFIG_SYS_NS87308_UART2   | \
 209                                   CONFIG_SYS_NS87308_POWRMAN | \
 210                                   CONFIG_SYS_NS87308_RTC_APC )
 211
 212 #undef  CONFIG_SYS_NS87308_PS2MOD
 213
 214 #define CONFIG_SYS_NS87308_CS0_BASE     0x0076
 215 #define CONFIG_SYS_NS87308_CS0_CONF     0x30
 216 #define CONFIG_SYS_NS87308_CS1_BASE     0x0075
 217 #define CONFIG_SYS_NS87308_CS1_CONF     0x30
 218 #define CONFIG_SYS_NS87308_CS2_BASE     0x0074
 219 #define CONFIG_SYS_NS87308_CS2_CONF     0x30
 220
 221 /*
 222  * NS16550 Configuration
 223  */
 224 #define CONFIG_SYS_NS16550
 225 #define CONFIG_SYS_NS16550_SERIAL
 226
 227 #define CONFIG_SYS_NS16550_REG_SIZE     1
 228
 229 #if (CONFIG_CONS_INDEX > 2)
 230 #define CONFIG_SYS_NS16550_CLK         CONFIG_DRAM_SPEED*1000000
 231 #else
 232 #define CONFIG_SYS_NS16550_CLK         1843200
 233 #endif
 234
 235 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
 236 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
 237 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
 238 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
 239
 240 /*
 241  * Low Level Configuration Settings
 242  * (address mappings, register initial values, etc.)
 243  * You should know what you are doing if you make changes here.
 244  */
 245
 246 #define CONFIG_SYS_CLK_FREQ  33333333   /* external frequency to pll */
 247
 248 #define CONFIG_SYS_ROMNAL               7       /*rom/flash next access time            */
 249 #define CONFIG_SYS_ROMFAL               11      /*rom/flash access time                 */
 250
 251 #define CONFIG_SYS_REFINT       430     /* no of clock cycles between CBR refresh cycles */
 252
 253 /* the following are for SDRAM only*/
 254 #define CONFIG_SYS_BSTOPRE      121     /* Burst To Precharge, sets open page interval */
 255 #define CONFIG_SYS_REFREC               8       /* Refresh to activate interval         */
 256 #define CONFIG_SYS_RDLAT                4       /* data latency from read command       */
 257 #define CONFIG_SYS_PRETOACT             3       /* Precharge to activate interval       */
 258 #define CONFIG_SYS_ACTTOPRE             5       /* Activate to Precharge interval       */
 259 #define CONFIG_SYS_ACTORW               3       /* Activate to R/W                      */
 260 #define CONFIG_SYS_SDMODE_CAS_LAT       3       /* SDMODE CAS latency                   */
 261 #define CONFIG_SYS_SDMODE_WRAP          0       /* SDMODE wrap type                     */
 262 #if 0
 263 #define CONFIG_SYS_SDMODE_BURSTLEN      2       /* OBSOLETE!  SDMODE Burst length 2=4, 3=8              */
 264 #endif
 265
 266 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
 267 #define CONFIG_SYS_EXTROM 1
 268 #define CONFIG_SYS_REGDIMM 0
 269
 270
 271 /* memory bank settings*/
 272 /*
 273  * only bits 20-29 are actually used from these vales to set the
 274  * start/end address the upper two bits will be 0, and the lower 20
 275  * bits will be set to 0x00000 for a start address, or 0xfffff for an
 276  * end address
 277  */
 278 #define CONFIG_SYS_BANK0_START          0x00000000
 279 #define CONFIG_SYS_BANK0_END            (CONFIG_SYS_MAX_RAM_SIZE - 1)
 280 #define CONFIG_SYS_BANK0_ENABLE 1
 281 #define CONFIG_SYS_BANK1_START          0x3ff00000
 282 #define CONFIG_SYS_BANK1_END            0x3fffffff
 283 #define CONFIG_SYS_BANK1_ENABLE 0
 284 #define CONFIG_SYS_BANK2_START          0x3ff00000
 285 #define CONFIG_SYS_BANK2_END            0x3fffffff
 286 #define CONFIG_SYS_BANK2_ENABLE 0
 287 #define CONFIG_SYS_BANK3_START          0x3ff00000
 288 #define CONFIG_SYS_BANK3_END            0x3fffffff
 289 #define CONFIG_SYS_BANK3_ENABLE 0
 290 #define CONFIG_SYS_BANK4_START          0x00000000
 291 #define CONFIG_SYS_BANK4_END            0x00000000
 292 #define CONFIG_SYS_BANK4_ENABLE 0
 293 #define CONFIG_SYS_BANK5_START          0x00000000
 294 #define CONFIG_SYS_BANK5_END            0x00000000
 295 #define CONFIG_SYS_BANK5_ENABLE 0
 296 #define CONFIG_SYS_BANK6_START          0x00000000
 297 #define CONFIG_SYS_BANK6_END            0x00000000
 298 #define CONFIG_SYS_BANK6_ENABLE 0
 299 #define CONFIG_SYS_BANK7_START          0x00000000
 300 #define CONFIG_SYS_BANK7_END            0x00000000
 301 #define CONFIG_SYS_BANK7_ENABLE 0
 302 /*
 303  * Memory bank enable bitmask, specifying which of the banks defined above
 304  are actually present. MSB is for bank #7, LSB is for bank #0.
 305  */
 306 #define CONFIG_SYS_BANK_ENABLE          0x01
 307
 308 #define CONFIG_SYS_ODCR         0xff    /* configures line driver impedances,   */
 309                                         /* see 8240 book for bit definitions    */
 310 #define CONFIG_SYS_PGMAX                0x32    /* how long the 8240 retains the        */
 311                                         /* currently accessed page in memory    */
 312                                         /* see 8240 book for details            */
 313
 314 /* SDRAM 0 - 256MB */
 315 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 316 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 317
 318 /* stack in DCACHE @ 1GB (no backing mem) */
 319 #if defined(USE_DINK32)
 320 #define CONFIG_SYS_IBAT1L       (0x40000000 | BATL_PP_00 )
 321 #define CONFIG_SYS_IBAT1U       (0x40000000 | BATU_BL_128K )
 322 #else
 323 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 324 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 325 #endif
 326
 327 /* PCI memory */
 328 #define CONFIG_SYS_IBAT2L       (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 329 #define CONFIG_SYS_IBAT2U       (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 330
 331 /* Flash, config addrs, etc */
 332 #define CONFIG_SYS_IBAT3L       (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 333 #define CONFIG_SYS_IBAT3U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 334
 335 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 336 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 337 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 338 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 339 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 340 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 341 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 342 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 343
 344 /*
 345  * For booting Linux, the board info and command line data
 346  * have to be in the first 8 MB of memory, since this is
 347  * the maximum mapped by the Linux kernel during initialization.
 348  */
 349 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 350 /*-----------------------------------------------------------------------
 351  * FLASH organization
 352  */
 353 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 354 #define CONFIG_SYS_MAX_FLASH_SECT       20      /* max number of sectors on one chip    */
 355
 356 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 357 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 358
 359 /*-----------------------------------------------------------------------
 360  * Cache Configuration
 361  */
 362 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8240 CPU                      */
 363 #if defined(CONFIG_CMD_KGDB)
 364 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 365 #endif
 366
 367 /* values according to the manual */
 368
 369 #define CONFIG_DRAM_50MHZ       1
 370 #define CONFIG_SDRAM_50MHZ
 371
 372 #undef  NR_8259_INTS
 373 #define NR_8259_INTS            1
 374
 375
 376 #define CONFIG_DISK_SPINUP_TIME 1000000
 377
 378
 379 #endif  /* __CONFIG_H */