include/configs/T208xQDS.h

   1 /*
   2  * Copyright 2011-2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * T2080/T2081 QDS board configuration file
   9  */
  10
  11 #ifndef __T208xQDS_H
  12 #define __T208xQDS_H
  13
  14 #define CONFIG_DISPLAY_BOARDINFO
  15 #define CONFIG_ICS307_REFCLK_HZ 25000000  /* ICS307 ref clk freq */
  16 #define CONFIG_MMC
  17 #define CONFIG_USB_EHCI
  18 #if defined(CONFIG_PPC_T2080)
  19 #define CONFIG_T2080QDS
  20 #define CONFIG_FSL_SATA_V2
  21 #define CONFIG_SYS_SRIO         /* Enable Serial RapidIO Support */
  22 #define CONFIG_SRIO1            /* SRIO port 1 */
  23 #define CONFIG_SRIO2            /* SRIO port 2 */
  24 #elif defined(CONFIG_PPC_T2081)
  25 #define CONFIG_T2081QDS
  26 #endif
  27
  28 /* High Level Configuration Options */
  29 #define CONFIG_BOOKE
  30 #define CONFIG_E500             /* BOOKE e500 family */
  31 #define CONFIG_E500MC           /* BOOKE e500mc family */
  32 #define CONFIG_SYS_BOOK3E_HV    /* Category E.HV supported */
  33 #define CONFIG_MP               /* support multiple processors */
  34 #define CONFIG_ENABLE_36BIT_PHYS
  35
  36 #ifdef CONFIG_PHYS_64BIT
  37 #define CONFIG_ADDR_MAP 1
  38 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  39 #endif
  40
  41 #define CONFIG_SYS_FSL_CPC      /* Corenet Platform Cache */
  42 #define CONFIG_SYS_NUM_CPC      CONFIG_NUM_DDR_CONTROLLERS
  43 #define CONFIG_FSL_IFC          /* Enable IFC Support */
  44 #define CONFIG_FSL_CAAM         /* Enable SEC/CAAM */
  45 #define CONFIG_FSL_LAW          /* Use common FSL init code */
  46 #define CONFIG_ENV_OVERWRITE
  47
  48 #ifdef CONFIG_RAMBOOT_PBL
  49 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg
  50 #if defined(CONFIG_PPC_T2080)
  51 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_rcw.cfg
  52 #elif defined(CONFIG_PPC_T2081)
  53 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_rcw.cfg
  54 #endif
  55
  56 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  57 #define CONFIG_SPL_SERIAL_SUPPORT
  58 #define CONFIG_SPL_FLUSH_IMAGE
  59 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  60 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  61 #define CONFIG_SYS_TEXT_BASE            0x00201000
  62 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  63 #define CONFIG_SPL_PAD_TO               0x40000
  64 #define CONFIG_SPL_MAX_SIZE             0x28000
  65 #define RESET_VECTOR_OFFSET             0x27FFC
  66 #define BOOT_PAGE_OFFSET                0x27000
  67 #ifdef CONFIG_SPL_BUILD
  68 #define CONFIG_SPL_SKIP_RELOCATE
  69 #define CONFIG_SPL_COMMON_INIT_DDR
  70 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  71 #define CONFIG_SYS_NO_FLASH
  72 #endif
  73
  74 #ifdef CONFIG_NAND
  75 #define CONFIG_SPL_NAND_SUPPORT
  76 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  77 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  78 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  79 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  80 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  81 #define CONFIG_SPL_NAND_BOOT
  82 #endif
  83
  84 #ifdef CONFIG_SPIFLASH
  85 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
  86 #define CONFIG_SPL_SPI_SUPPORT
  87 #define CONFIG_SPL_SPI_FLASH_SUPPORT
  88 #define CONFIG_SPL_SPI_FLASH_MINIMAL
  89 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
  90 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x00200000)
  91 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x00200000)
  92 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
  93 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
  94 #ifndef CONFIG_SPL_BUILD
  95 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
  96 #endif
  97 #define CONFIG_SPL_SPI_BOOT
  98 #endif
  99
 100 #ifdef CONFIG_SDCARD
 101 #define CONFIG_RESET_VECTOR_ADDRESS             0x200FFC
 102 #define CONFIG_SPL_MMC_MINIMAL
 103 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
 104 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x00200000)
 105 #define CONFIG_SYS_MMC_U_BOOT_START     (0x00200000)
 106 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
 107 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot.lds"
 108 #ifndef CONFIG_SPL_BUILD
 109 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
 110 #endif
 111 #define CONFIG_SPL_MMC_BOOT
 112 #endif
 113
 114 #endif /* CONFIG_RAMBOOT_PBL */
 115
 116 #define CONFIG_SRIO_PCIE_BOOT_MASTER
 117 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 118 /* Set 1M boot space */
 119 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
 120 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
 121                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
 122 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
 123 #define CONFIG_SYS_NO_FLASH
 124 #endif
 125
 126 #ifndef CONFIG_SYS_TEXT_BASE
 127 #define CONFIG_SYS_TEXT_BASE    0xeff40000
 128 #endif
 129
 130 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 131 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
 132 #endif
 133
 134 /*
 135  * These can be toggled for performance analysis, otherwise use default.
 136  */
 137 #define CONFIG_SYS_CACHE_STASHING
 138 #define CONFIG_BTB              /* toggle branch predition */
 139 #define CONFIG_DDR_ECC
 140 #ifdef CONFIG_DDR_ECC
 141 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 142 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 143 #endif
 144
 145 #ifndef CONFIG_SYS_NO_FLASH
 146 #define CONFIG_FLASH_CFI_DRIVER
 147 #define CONFIG_SYS_FLASH_CFI
 148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 149 #endif
 150
 151 #if defined(CONFIG_SPIFLASH)
 152 #define CONFIG_SYS_EXTRA_ENV_RELOC
 153 #define CONFIG_ENV_IS_IN_SPI_FLASH
 154 #define CONFIG_ENV_SPI_BUS      0
 155 #define CONFIG_ENV_SPI_CS       0
 156 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 157 #define CONFIG_ENV_SPI_MODE     0
 158 #define CONFIG_ENV_SIZE         0x2000     /* 8KB */
 159 #define CONFIG_ENV_OFFSET       0x100000   /* 1MB */
 160 #define CONFIG_ENV_SECT_SIZE    0x10000
 161 #elif defined(CONFIG_SDCARD)
 162 #define CONFIG_SYS_EXTRA_ENV_RELOC
 163 #define CONFIG_ENV_IS_IN_MMC
 164 #define CONFIG_SYS_MMC_ENV_DEV  0
 165 #define CONFIG_ENV_SIZE         0x2000
 166 #define CONFIG_ENV_OFFSET       (512 * 0x800)
 167 #elif defined(CONFIG_NAND)
 168 #define CONFIG_SYS_EXTRA_ENV_RELOC
 169 #define CONFIG_ENV_IS_IN_NAND
 170 #define CONFIG_ENV_SIZE         0x2000
 171 #define CONFIG_ENV_OFFSET       (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 172 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 173 #define CONFIG_ENV_IS_IN_REMOTE
 174 #define CONFIG_ENV_ADDR         0xffe20000
 175 #define CONFIG_ENV_SIZE         0x2000
 176 #elif defined(CONFIG_ENV_IS_NOWHERE)
 177 #define CONFIG_ENV_SIZE         0x2000
 178 #else
 179 #define CONFIG_ENV_IS_IN_FLASH
 180 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 181 #define CONFIG_ENV_SIZE         0x2000
 182 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 183 #endif
 184
 185 #ifndef __ASSEMBLY__
 186 unsigned long get_board_sys_clk(void);
 187 unsigned long get_board_ddr_clk(void);
 188 #endif
 189
 190 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk()
 191 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 192
 193 /*
 194  * Config the L3 Cache as L3 SRAM
 195  */
 196 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 197 #define CONFIG_SYS_L3_SIZE              (512 << 10)
 198 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 199 #ifdef CONFIG_RAMBOOT_PBL
 200 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 201 #endif
 202 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 203 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (50 << 10)
 204 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 205 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 206
 207 #define CONFIG_SYS_DCSRBAR      0xf0000000
 208 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
 209
 210 /* EEPROM */
 211 #define CONFIG_ID_EEPROM
 212 #define CONFIG_SYS_I2C_EEPROM_NXID
 213 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 214 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 215 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 216
 217 /*
 218  * DDR Setup
 219  */
 220 #define CONFIG_VERY_BIG_RAM
 221 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 222 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 223 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
 224 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
 225 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 226 #define CONFIG_DDR_SPD
 227 #define CONFIG_SYS_FSL_DDR3
 228 #define CONFIG_FSL_DDR_INTERACTIVE
 229 #define CONFIG_SYS_SPD_BUS_NUM  0
 230 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 231 #define SPD_EEPROM_ADDRESS1     0x51
 232 #define SPD_EEPROM_ADDRESS2     0x52
 233 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 234 #define CTRL_INTLV_PREFERED     cacheline
 235
 236 /*
 237  * IFC Definitions
 238  */
 239 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 240 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 241 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 242 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 243                                 + 0x8000000) | \
 244                                 CSPR_PORT_SIZE_16 | \
 245                                 CSPR_MSEL_NOR | \
 246                                 CSPR_V)
 247 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 248 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 249                                 CSPR_PORT_SIZE_16 | \
 250                                 CSPR_MSEL_NOR | \
 251                                 CSPR_V)
 252 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 253 /* NOR Flash Timing Params */
 254 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
 255
 256 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
 257                                 FTIM0_NOR_TEADC(0x5) | \
 258                                 FTIM0_NOR_TEAHC(0x5))
 259 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 260                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 261                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 262 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
 263                                 FTIM2_NOR_TCH(0x4) | \
 264                                 FTIM2_NOR_TWPH(0x0E) | \
 265                                 FTIM2_NOR_TWP(0x1c))
 266 #define CONFIG_SYS_NOR_FTIM3    0x0
 267
 268 #define CONFIG_SYS_FLASH_QUIET_TEST
 269 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 270
 271 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 272 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 273 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 274 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 275
 276 #define CONFIG_SYS_FLASH_EMPTY_INFO
 277 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 278                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 279
 280 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 281 #define QIXIS_BASE                      0xffdf0000
 282 #define QIXIS_LBMAP_SWITCH              6
 283 #define QIXIS_LBMAP_MASK                0x0f
 284 #define QIXIS_LBMAP_SHIFT               0
 285 #define QIXIS_LBMAP_DFLTBANK            0x00
 286 #define QIXIS_LBMAP_ALTBANK             0x04
 287 #define QIXIS_LBMAP_NAND                0x09
 288 #define QIXIS_LBMAP_SD                  0x00
 289 #define QIXIS_RCW_SRC_NAND              0x104
 290 #define QIXIS_RCW_SRC_SD                0x040
 291 #define QIXIS_RST_CTL_RESET             0x83
 292 #define QIXIS_RST_FORCE_MEM             0x1
 293 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 294 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 295 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 296 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 297
 298 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 299 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 300                                 | CSPR_PORT_SIZE_8 \
 301                                 | CSPR_MSEL_GPCM \
 302                                 | CSPR_V)
 303 #define CONFIG_SYS_AMASK3       IFC_AMASK(4*1024)
 304 #define CONFIG_SYS_CSOR3        0x0
 305 /* QIXIS Timing parameters for IFC CS3 */
 306 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 307                                         FTIM0_GPCM_TEADC(0x0e) | \
 308                                         FTIM0_GPCM_TEAHC(0x0e))
 309 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 310                                         FTIM1_GPCM_TRAD(0x3f))
 311 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 312                                         FTIM2_GPCM_TCH(0x8) | \
 313                                         FTIM2_GPCM_TWP(0x1f))
 314 #define CONFIG_SYS_CS3_FTIM3            0x0
 315
 316 /* NAND Flash on IFC */
 317 #define CONFIG_NAND_FSL_IFC
 318 #define CONFIG_SYS_NAND_BASE            0xff800000
 319 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 320
 321 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 322 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 323                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 324                                 | CSPR_MSEL_NAND         /* MSEL = NAND */ \
 325                                 | CSPR_V)
 326 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 327
 328 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 329                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 330                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */     \
 331                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */   \
 332                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */\
 333                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */\
 334                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 335
 336 #define CONFIG_SYS_NAND_ONFI_DETECTION
 337
 338 /* ONFI NAND Flash mode0 Timing Params */
 339 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 340                                         FTIM0_NAND_TWP(0x18)    | \
 341                                         FTIM0_NAND_TWCHT(0x07)  | \
 342                                         FTIM0_NAND_TWH(0x0a))
 343 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 344                                         FTIM1_NAND_TWBE(0x39)   | \
 345                                         FTIM1_NAND_TRR(0x0e)    | \
 346                                         FTIM1_NAND_TRP(0x18))
 347 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f)  | \
 348                                         FTIM2_NAND_TREH(0x0a)   | \
 349                                         FTIM2_NAND_TWHRE(0x1e))
 350 #define CONFIG_SYS_NAND_FTIM3           0x0
 351
 352 #define CONFIG_SYS_NAND_DDR_LAW         11
 353 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 354 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 355 #define CONFIG_CMD_NAND
 356 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 357
 358 #if defined(CONFIG_NAND)
 359 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 360 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 361 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 362 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 363 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 364 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 365 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 366 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 367 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 368 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 369 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 370 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 371 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 372 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 373 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 374 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 375 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 376 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 377 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 378 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 379 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 380 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 381 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 382 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 383 #else
 384 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 385 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 386 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 387 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 388 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 389 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 390 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 391 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 392 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 393 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 394 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 395 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 396 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 397 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 398 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 399 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 400 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 401 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 402 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 403 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 404 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 405 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 406 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 407 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 408 #endif
 409
 410 #if defined(CONFIG_RAMBOOT_PBL)
 411 #define CONFIG_SYS_RAMBOOT
 412 #endif
 413
 414 #ifdef CONFIG_SPL_BUILD
 415 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 416 #else
 417 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 418 #endif
 419
 420 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 421 #define CONFIG_MISC_INIT_R
 422 #define CONFIG_HWCONFIG
 423
 424 /* define to use L1 as initial stack */
 425 #define CONFIG_L1_INIT_RAM
 426 #define CONFIG_SYS_INIT_RAM_LOCK
 427 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000 /* Initial L1 address */
 428 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 429 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 430 /* The assembler doesn't like typecast */
 431 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 432                         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 433                         CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 434 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 435 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 436                                                 GENERATED_GBL_DATA_SIZE)
 437 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 438 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 439 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 440
 441 /*
 442  * Serial Port
 443  */
 444 #define CONFIG_CONS_INDEX               1
 445 #define CONFIG_SYS_NS16550_SERIAL
 446 #define CONFIG_SYS_NS16550_REG_SIZE     1
 447 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 448 #define CONFIG_SYS_BAUDRATE_TABLE       \
 449         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 450 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 451 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 452 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 453 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 454
 455 /*
 456  * I2C
 457  */
 458 #define CONFIG_SYS_I2C
 459 #define CONFIG_SYS_I2C_FSL
 460 #define CONFIG_SYS_FSL_I2C_SLAVE   0x7F
 461 #define CONFIG_SYS_FSL_I2C2_SLAVE  0x7F
 462 #define CONFIG_SYS_FSL_I2C3_SLAVE  0x7F
 463 #define CONFIG_SYS_FSL_I2C4_SLAVE  0x7F
 464 #define CONFIG_SYS_FSL_I2C_OFFSET  0x118000
 465 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
 466 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
 467 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
 468 #define CONFIG_SYS_FSL_I2C_SPEED   100000
 469 #define CONFIG_SYS_FSL_I2C2_SPEED  100000
 470 #define CONFIG_SYS_FSL_I2C3_SPEED  100000
 471 #define CONFIG_SYS_FSL_I2C4_SPEED  100000
 472 #define I2C_MUX_PCA_ADDR_PRI    0x77 /* I2C bus multiplexer,primary */
 473 #define I2C_MUX_PCA_ADDR_SEC1   0x75 /* I2C bus multiplexer,secondary 1 */
 474 #define I2C_MUX_PCA_ADDR_SEC2   0x76 /* I2C bus multiplexer,secondary 2 */
 475 #define I2C_MUX_CH_DEFAULT      0x8
 476
 477 #define I2C_MUX_CH_VOL_MONITOR 0xa
 478
 479 /* Voltage monitor on channel 2*/
 480 #define I2C_VOL_MONITOR_ADDR           0x40
 481 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 482 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 483 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 484
 485 #define CONFIG_VID_FLS_ENV              "t208xqds_vdd_mv"
 486 #ifndef CONFIG_SPL_BUILD
 487 #define CONFIG_VID
 488 #endif
 489 #define CONFIG_VOL_MONITOR_IR36021_SET
 490 #define CONFIG_VOL_MONITOR_IR36021_READ
 491 /* The lowest and highest voltage allowed for T208xQDS */
 492 #define VDD_MV_MIN                      819
 493 #define VDD_MV_MAX                      1212
 494
 495 /*
 496  * RapidIO
 497  */
 498 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 499 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 500 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000 /* 256M */
 501 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 502 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 503 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000 /* 256M */
 504 /*
 505  * for slave u-boot IMAGE instored in master memory space,
 506  * PHYS must be aligned based on the SIZE
 507  */
 508 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 509 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 510 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
 511 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 512 /*
 513  * for slave UCODE and ENV instored in master memory space,
 514  * PHYS must be aligned based on the SIZE
 515  */
 516 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 517 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 518 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
 519
 520 /* slave core release by master*/
 521 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 522 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 523
 524 /*
 525  * SRIO_PCIE_BOOT - SLAVE
 526  */
 527 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 528 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 529 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 530                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 531 #endif
 532
 533 /*
 534  * eSPI - Enhanced SPI
 535  */
 536 #ifdef CONFIG_SPI_FLASH
 537 #ifndef CONFIG_SPL_BUILD
 538 #endif
 539
 540 #define CONFIG_SPI_FLASH_BAR
 541 #define CONFIG_SF_DEFAULT_SPEED  10000000
 542 #define CONFIG_SF_DEFAULT_MODE    0
 543 #endif
 544
 545 /*
 546  * General PCI
 547  * Memory space is mapped 1-1, but I/O space must start from 0.
 548  */
 549 #define CONFIG_PCI              /* Enable PCI/PCIE */
 550 #define CONFIG_PCIE1            /* PCIE controller 1 */
 551 #define CONFIG_PCIE2            /* PCIE controller 2 */
 552 #define CONFIG_PCIE3            /* PCIE controller 3 */
 553 #define CONFIG_PCIE4            /* PCIE controller 4 */
 554 #define CONFIG_FSL_PCIE_RESET
 555 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
 556 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
 557 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 558 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 559 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 560 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 561 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 562 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 563 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 564 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 565 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 566
 567 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 568 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 569 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 570 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 571 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x10000000 /* 256M */
 572 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 573 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 574 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 575 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 576
 577 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 578 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xb0000000
 579 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 580 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc30000000ull
 581 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x10000000      /* 256M */
 582 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 583 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 584 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 585 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 586
 587 /* controller 4, Base address 203000 */
 588 #define CONFIG_SYS_PCIE4_MEM_VIRT       0xc0000000
 589 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 590 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc40000000ull
 591 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x10000000      /* 256M */
 592 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 593 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 594 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 595
 596 #ifdef CONFIG_PCI
 597 #define CONFIG_PCI_INDIRECT_BRIDGE
 598 #define CONFIG_FSL_PCIE_RESET      /* need PCIe reset errata */
 599 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 600 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 601 #define CONFIG_DOS_PARTITION
 602 #endif
 603
 604 /* Qman/Bman */
 605 #ifndef CONFIG_NOBQFMAN
 606 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 607 #define CONFIG_SYS_BMAN_NUM_PORTALS     18
 608 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 609 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 610 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 611 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 612 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 613 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 614 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 615 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 616                                         CONFIG_SYS_BMAN_CENA_SIZE)
 617 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 618 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 619 #define CONFIG_SYS_QMAN_NUM_PORTALS     18
 620 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 621 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 622 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 623 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 624 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 625 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 626 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 627 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 628                                         CONFIG_SYS_QMAN_CENA_SIZE)
 629 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 630 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 631
 632 #define CONFIG_SYS_DPAA_FMAN
 633 #define CONFIG_SYS_DPAA_PME
 634 #define CONFIG_SYS_PMAN
 635 #define CONFIG_SYS_DPAA_DCE
 636 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
 637 #define CONFIG_SYS_INTERLAKEN
 638
 639 /* Default address of microcode for the Linux Fman driver */
 640 #if defined(CONFIG_SPIFLASH)
 641 /*
 642  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 643  * env, so we got 0x110000.
 644  */
 645 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 646 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 647 #elif defined(CONFIG_SDCARD)
 648 /*
 649  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 650  * about 1MB (2048 blocks), Env is stored after the image, and the env size is
 651  * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
 652  */
 653 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 654 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
 655 #elif defined(CONFIG_NAND)
 656 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 657 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
 658 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 659 /*
 660  * Slave has no ucode locally, it can fetch this from remote. When implementing
 661  * in two corenet boards, slave's ucode could be stored in master's memory
 662  * space, the address can be mapped from slave TLB->slave LAW->
 663  * slave SRIO or PCIE outbound window->master inbound window->
 664  * master LAW->the ucode address in master's memory space.
 665  */
 666 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 667 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 668 #else
 669 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 670 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
 671 #endif
 672 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 673 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 674 #endif /* CONFIG_NOBQFMAN */
 675
 676 #ifdef CONFIG_SYS_DPAA_FMAN
 677 #define CONFIG_FMAN_ENET
 678 #define CONFIG_PHYLIB_10G
 679 #define CONFIG_PHY_VITESSE
 680 #define CONFIG_PHY_REALTEK
 681 #define CONFIG_PHY_TERANETICS
 682 #define RGMII_PHY1_ADDR 0x1
 683 #define RGMII_PHY2_ADDR 0x2
 684 #define FM1_10GEC1_PHY_ADDR       0x3
 685 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 686 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
 687 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 688 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
 689 #endif
 690
 691 #ifdef CONFIG_FMAN_ENET
 692 #define CONFIG_MII              /* MII PHY management */
 693 #define CONFIG_ETHPRIME         "FM1@DTSEC3"
 694 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 695 #endif
 696
 697 /*
 698  * SATA
 699  */
 700 #ifdef CONFIG_FSL_SATA_V2
 701 #define CONFIG_LIBATA
 702 #define CONFIG_FSL_SATA
 703 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 704 #define CONFIG_SATA1
 705 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 706 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 707 #define CONFIG_SATA2
 708 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 709 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 710 #define CONFIG_LBA48
 711 #define CONFIG_CMD_SATA
 712 #define CONFIG_DOS_PARTITION
 713 #endif
 714
 715 /*
 716  * USB
 717  */
 718 #ifdef CONFIG_USB_EHCI
 719 #define CONFIG_USB_EHCI_FSL
 720 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 721 #define CONFIG_HAS_FSL_DR_USB
 722 #endif
 723
 724 /*
 725  * SDHC
 726  */
 727 #ifdef CONFIG_MMC
 728 #define CONFIG_FSL_ESDHC
 729 #define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 730 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 731 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 732 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 733 #define CONFIG_GENERIC_MMC
 734 #define CONFIG_DOS_PARTITION
 735 #define CONFIG_FSL_ESDHC_ADAPTER_IDENT
 736 #endif
 737
 738 /*
 739  * Dynamic MTD Partition support with mtdparts
 740  */
 741 #ifndef CONFIG_SYS_NO_FLASH
 742 #define CONFIG_MTD_DEVICE
 743 #define CONFIG_MTD_PARTITIONS
 744 #define CONFIG_CMD_MTDPARTS
 745 #define CONFIG_FLASH_CFI_MTD
 746 #define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
 747                         "spi0=spife110000.0"
 748 #define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
 749                         "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
 750                         "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:" \
 751                         "1m(uboot),5m(kernel),128k(dtb),-(user)"
 752 #endif
 753
 754 /*
 755  * Environment
 756  */
 757 #define CONFIG_LOADS_ECHO       /* echo on for serial download */
 758 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 759
 760 /*
 761  * Command line configuration.
 762  */
 763 #define CONFIG_CMD_ERRATA
 764 #define CONFIG_CMD_IRQ
 765 #define CONFIG_CMD_REGINFO
 766
 767 #ifdef CONFIG_PCI
 768 #define CONFIG_CMD_PCI
 769 #endif
 770
 771 /* Hash command with SHA acceleration supported in hardware */
 772 #ifdef CONFIG_FSL_CAAM
 773 #define CONFIG_CMD_HASH
 774 #define CONFIG_SHA_HW_ACCEL
 775 #endif
 776
 777 /*
 778  * Miscellaneous configurable options
 779  */
 780 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 781 #define CONFIG_CMDLINE_EDITING          /* Command-line editing */
 782 #define CONFIG_AUTO_COMPLETE            /* add autocompletion support */
 783 #define CONFIG_SYS_LOAD_ADDR    0x2000000 /* default load address */
 784 #ifdef CONFIG_CMD_KGDB
 785 #define CONFIG_SYS_CBSIZE       1024      /* Console I/O Buffer Size */
 786 #else
 787 #define CONFIG_SYS_CBSIZE       256       /* Console I/O Buffer Size */
 788 #endif
 789 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 790 #define CONFIG_SYS_MAXARGS      16      /* max number of command args */
 791 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 792
 793 /*
 794  * For booting Linux, the board info and command line data
 795  * have to be in the first 64 MB of memory, since this is
 796  * the maximum mapped by the Linux kernel during initialization.
 797  */
 798 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 799 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 800
 801 #ifdef CONFIG_CMD_KGDB
 802 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 803 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 804 #endif
 805
 806 /*
 807  * Environment Configuration
 808  */
 809 #define CONFIG_ROOTPATH  "/opt/nfsroot"
 810 #define CONFIG_BOOTFILE  "uImage"
 811 #define CONFIG_UBOOTPATH "u-boot.bin"   /* U-Boot image on TFTP server */
 812
 813 /* default location for tftp and bootm */
 814 #define CONFIG_LOADADDR         1000000
 815 #define CONFIG_BAUDRATE         115200
 816 #define __USB_PHY_TYPE          utmi
 817
 818 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 819         "hwconfig=fsl_ddr:"                                     \
 820         "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) ","      \
 821         "bank_intlv=auto;"                                      \
 822         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 823         "netdev=eth0\0"                                         \
 824         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
 825         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
 826         "tftpflash=tftpboot $loadaddr $uboot && "               \
 827         "protect off $ubootaddr +$filesize && "                 \
 828         "erase $ubootaddr +$filesize && "                       \
 829         "cp.b $loadaddr $ubootaddr $filesize && "               \
 830         "protect on $ubootaddr +$filesize && "                  \
 831         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 832         "consoledev=ttyS0\0"                                    \
 833         "ramdiskaddr=2000000\0"                                 \
 834         "ramdiskfile=t2080qds/ramdisk.uboot\0"                  \
 835         "fdtaddr=1e00000\0"                                     \
 836         "fdtfile=t2080qds/t2080qds.dtb\0"                       \
 837         "bdev=sda3\0"
 838
 839 /*
 840  * For emulation this causes u-boot to jump to the start of the
 841  * proof point app code automatically
 842  */
 843 #define CONFIG_PROOF_POINTS                             \
 844         "setenv bootargs root=/dev/$bdev rw "           \
 845         "console=$consoledev,$baudrate $othbootargs;"   \
 846         "cpu 1 release 0x29000000 - - -;"               \
 847         "cpu 2 release 0x29000000 - - -;"               \
 848         "cpu 3 release 0x29000000 - - -;"               \
 849         "cpu 4 release 0x29000000 - - -;"               \
 850         "cpu 5 release 0x29000000 - - -;"               \
 851         "cpu 6 release 0x29000000 - - -;"               \
 852         "cpu 7 release 0x29000000 - - -;"               \
 853         "go 0x29000000"
 854
 855 #define CONFIG_HVBOOT                           \
 856         "setenv bootargs config-addr=0x60000000; "      \
 857         "bootm 0x01000000 - 0x00f00000"
 858
 859 #define CONFIG_ALU                              \
 860         "setenv bootargs root=/dev/$bdev rw "           \
 861         "console=$consoledev,$baudrate $othbootargs;"   \
 862         "cpu 1 release 0x01000000 - - -;"               \
 863         "cpu 2 release 0x01000000 - - -;"               \
 864         "cpu 3 release 0x01000000 - - -;"               \
 865         "cpu 4 release 0x01000000 - - -;"               \
 866         "cpu 5 release 0x01000000 - - -;"               \
 867         "cpu 6 release 0x01000000 - - -;"               \
 868         "cpu 7 release 0x01000000 - - -;"               \
 869         "go 0x01000000"
 870
 871 #define CONFIG_LINUX                            \
 872         "setenv bootargs root=/dev/ram rw "             \
 873         "console=$consoledev,$baudrate $othbootargs;"   \
 874         "setenv ramdiskaddr 0x02000000;"                \
 875         "setenv fdtaddr 0x00c00000;"                    \
 876         "setenv loadaddr 0x1000000;"                    \
 877         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 878
 879 #define CONFIG_HDBOOT                                   \
 880         "setenv bootargs root=/dev/$bdev rw "           \
 881         "console=$consoledev,$baudrate $othbootargs;"   \
 882         "tftp $loadaddr $bootfile;"                     \
 883         "tftp $fdtaddr $fdtfile;"                       \
 884         "bootm $loadaddr - $fdtaddr"
 885
 886 #define CONFIG_NFSBOOTCOMMAND                   \
 887         "setenv bootargs root=/dev/nfs rw "     \
 888         "nfsroot=$serverip:$rootpath "          \
 889         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 890         "console=$consoledev,$baudrate $othbootargs;"   \
 891         "tftp $loadaddr $bootfile;"             \
 892         "tftp $fdtaddr $fdtfile;"               \
 893         "bootm $loadaddr - $fdtaddr"
 894
 895 #define CONFIG_RAMBOOTCOMMAND                           \
 896         "setenv bootargs root=/dev/ram rw "             \
 897         "console=$consoledev,$baudrate $othbootargs;"   \
 898         "tftp $ramdiskaddr $ramdiskfile;"               \
 899         "tftp $loadaddr $bootfile;"                     \
 900         "tftp $fdtaddr $fdtfile;"                       \
 901         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 902
 903 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 904
 905 #include <asm/fsl_secure_boot.h>
 906
 907 #endif  /* __T208xQDS_H */