include/configs/TASREG.h

   1 /*
   2  * Configuation settings for the esd TASREG board.
   3  *
   4  * (C) Copyright 2004
   5  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _TASREG_H
  15 #define _TASREG_H
  16
  17 #ifndef __ASSEMBLY__
  18 #include <asm/m5249.h>
  19 #endif
  20
  21 /*
  22  * High Level Configuration Options
  23  * (easy to change)
  24  */
  25 #define CONFIG_MCF52x2                  /* define processor family */
  26 #define CONFIG_M5249                    /* define processor type */
  27
  28 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  29
  30 #define CONFIG_MCFTMR
  31
  32 #define CONFIG_MCFUART
  33 #define CONFIG_SYS_UART_PORT            (0)
  34 #define CONFIG_BAUDRATE         19200
  35
  36 #undef  CONFIG_WATCHDOG
  37
  38 #undef CONFIG_MONITOR_IS_IN_RAM               /* no pre-loader required!!! ;-) */
  39
  40
  41 /*
  42  * BOOTP options
  43  */
  44 #define CONFIG_BOOTP_BOOTFILESIZE
  45 #define CONFIG_BOOTP_BOOTPATH
  46 #define CONFIG_BOOTP_GATEWAY
  47 #define CONFIG_BOOTP_HOSTNAME
  48
  49
  50 /*
  51  * Command line configuration.
  52  */
  53 #include <config_cmd_default.h>
  54
  55 #define CONFIG_CMD_BSP
  56 #define CONFIG_CMD_EEPROM
  57 #define CONFIG_CMD_I2C
  58
  59 #undef CONFIG_CMD_NET
  60
  61
  62 #define CONFIG_BOOTDELAY        3
  63
  64 #define CONFIG_SYS_PROMPT               "=> "
  65 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
  66
  67 #if defined(CONFIG_CMD_KGDB)
  68 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size      */
  69 #else
  70 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  71 #endif
  72 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  73 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
  74 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  75
  76 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  77 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
  78 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
  79 #define CONFIG_LOOPW            1       /* enable loopw command         */
  80 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
  81
  82 #define CONFIG_SYS_LOAD_ADDR            0x200000        /* default load address */
  83
  84 #define CONFIG_SYS_MEMTEST_START        0x400
  85 #define CONFIG_SYS_MEMTEST_END          0x380000
  86
  87 #define CONFIG_SYS_HZ                   1000
  88
  89 /*
  90  * Clock configuration: enable only one of the following options
  91  */
  92
  93 #if 0 /* this setting will run the cpu at 11MHz */
  94 #define CONFIG_SYS_PLL_BYPASS          1                /* bypass PLL for test purpose */
  95 #undef  CONFIG_SYS_FAST_CLK                             /* MCF5249 can run at 140MHz   */
  96 #define CONFIG_SYS_CLK                  11289600         /* PLL bypass                  */
  97 #endif
  98
  99 #if 0 /* this setting will run the cpu at 70MHz */
 100 #undef  CONFIG_SYS_PLL_BYPASS                           /* bypass PLL for test purpose */
 101 #undef  CONFIG_SYS_FAST_CLK                             /* MCF5249 can run at 140MHz   */
 102 #define CONFIG_SYS_CLK                  72185018         /* The next lower speed        */
 103 #endif
 104
 105 #if 1 /* this setting will run the cpu at 140MHz */
 106 #undef  CONFIG_SYS_PLL_BYPASS                           /* bypass PLL for test purpose */
 107 #define CONFIG_SYS_FAST_CLK            1                /* MCF5249 can run at 140MHz   */
 108 #define CONFIG_SYS_CLK                  132025600        /* MCF5249 can run at 140MHz   */
 109 #endif
 110
 111 /*
 112  * Low Level Configuration Settings
 113  * (address mappings, register initial values, etc.)
 114  * You should know what you are doing if you make changes here.
 115  */
 116
 117 #define CONFIG_SYS_MBAR         0x10000000      /* Register Base Addrs */
 118 #define CONFIG_SYS_MBAR2                0x80000000
 119
 120 /*-----------------------------------------------------------------------
 121  * I2C
 122  */
 123 #define CONFIG_SOFT_I2C
 124 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 125 #define CONFIG_SYS_I2C_SLAVE            0x7F
 126 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC32             */
 127 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2        /* Bytes of address             */
 128 /* mask of address bits that overflow into the "EEPROM chip address"    */
 129 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x01
 130 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5     /* The Catalyst CAT24WC32 has   */
 131                                         /* 32 byte page write mode using*/
 132                                         /* last 5 bits of the address   */
 133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 134
 135 #if defined (CONFIG_SOFT_I2C)
 136 #if 0 /* push-pull */
 137 #define SDA             0x00800000
 138 #define SCL             0x00000008
 139 #define DIR0            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
 140 #define DIR1            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
 141 #define OUT0            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
 142 #define OUT1            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
 143 #define IN0             *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
 144 #define IN1             *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
 145 #define I2C_INIT        {OUT1|=SDA;OUT0|=SCL;}
 146 #define I2C_READ        ((IN1&SDA)?1:0)
 147 #define I2C_SDA(x)      {if(x)OUT1|=SDA;else OUT1&=~SDA;}
 148 #define I2C_SCL(x)      {if(x)OUT0|=SCL;else OUT0&=~SCL;}
 149 #define I2C_DELAY       {udelay(5);}
 150 #define I2C_ACTIVE      {DIR1|=SDA;}
 151 #define I2C_TRISTATE    {DIR1&=~SDA;}
 152 #else /* open-collector */
 153 #define SDA             0x00800000
 154 #define SCL             0x00000008
 155 #define DIR0            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_EN))
 156 #define DIR1            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_EN))
 157 #define OUT0            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_OUT))
 158 #define OUT1            *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_OUT))
 159 #define IN0             *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO_READ))
 160 #define IN1             *((volatile ulong*)(CONFIG_SYS_MBAR2+MCFSIM_GPIO1_READ))
 161 #define I2C_INIT        {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
 162 #define I2C_READ        ((IN1&SDA)?1:0)
 163 #define I2C_SDA(x)      {if(x)DIR1&=~SDA;else DIR1|=SDA;}
 164 #define I2C_SCL(x)      {if(x)DIR0&=~SCL;else DIR0|=SCL;}
 165 #define I2C_DELAY       {udelay(5);}
 166 #define I2C_ACTIVE      {DIR1|=SDA;}
 167 #define I2C_TRISTATE    {DIR1&=~SDA;}
 168 #endif
 169 #endif
 170
 171 /*-----------------------------------------------------------------------
 172  * Definitions for initial stack pointer and data area (in DPRAM)
 173  */
 174 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 175 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in internal SRAM   */
 176 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 177 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 178
 179 #define CONFIG_ENV_IS_IN_FLASH  1
 180 #define CONFIG_ENV_ADDR         0xFFC40000      /* Address of Environment Sector*/
 181 #define CONFIG_ENV_SIZE         0x10000 /* Total Size of Environment Sector     */
 182 #define CONFIG_ENV_SECT_SIZE    0x10000 /* see README - env sector total size   */
 183
 184 /*-----------------------------------------------------------------------
 185  * Start addresses for the final memory configuration
 186  * (Set up by the startup code)
 187  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 188  */
 189 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 190 #define CONFIG_SYS_SDRAM_SIZE           16              /* SDRAM size in MB */
 191 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 192
 193 #if 0 /* test-only */
 194 #define CONFIG_PRAM             512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
 195 #endif
 196
 197 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 198
 199 #define CONFIG_SYS_MONITOR_LEN          0x20000
 200 #define CONFIG_SYS_MALLOC_LEN           (1 * 1024*1024) /* Reserve 1 MB for malloc()    */
 201 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 202
 203 /*
 204  * For booting Linux, the board info and command line data
 205  * have to be in the first 8 MB of memory, since this is
 206  * the maximum mapped by the Linux kernel during initialization ??
 207  */
 208 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 209
 210 /*-----------------------------------------------------------------------
 211  * FLASH organization
 212  */
 213 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 214 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 215
 216 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 217 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 218
 219 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 220 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 221 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 222 /*
 223  * The following defines are added for buggy IOP480 byte interface.
 224  * All other boards should use the standard values (CPCI405 etc.)
 225  */
 226 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 227 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 228 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 229
 230 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 231
 232 /*-----------------------------------------------------------------------
 233  * Cache Configuration
 234  */
 235 #define CONFIG_SYS_CACHELINE_SIZE       16
 236
 237 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 238                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 239 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 240                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 241 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_DCM)
 242 #define CONFIG_SYS_CACHE_ACR1           (CONFIG_SYS_SDRAM_BASE | \
 243                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 244                                          CF_ACR_EN | CF_ACR_SM_ALL)
 245 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CEIB | \
 246                                          CF_CACR_DBWE)
 247
 248 /*-----------------------------------------------------------------------
 249  * Memory bank definitions
 250  */
 251
 252 /* CS0 - AMD Flash, address 0xffc00000 */
 253 #define CONFIG_SYS_CS0_BASE             0xffc00000
 254 #define CONFIG_SYS_CS0_CTRL             0x00001980      /* WS=0110, AA=1, PS=10         */
 255 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
 256 #define CONFIG_SYS_CS0_MASK             0x003f0021      /* 4MB, AA=0, WP=0, C/I=1, V=1  */
 257
 258 /* CS1 - FPGA, address 0xe0000000 */
 259 #define CONFIG_SYS_CS1_BASE             0xe0000000
 260 #define CONFIG_SYS_CS1_CTRL             0x00000d80      /* WS=0011, AA=1, PS=10         */
 261 #define CONFIG_SYS_CS1_MASK             0x00010001      /* 128kB, AA=0, WP=0, C/I=0, V=1*/
 262
 263 /*-----------------------------------------------------------------------
 264  * Port configuration
 265  */
 266 #define CONFIG_SYS_GPIO_FUNC           0x00000008      /* Set gpio pins: none          */
 267 #define CONFIG_SYS_GPIO1_FUNC          0x00df00f0      /* 36-39(SWITCH),48-52(FPGAs),54*/
 268 #define CONFIG_SYS_GPIO_EN             0x00000008      /* Set gpio output enable       */
 269 #define CONFIG_SYS_GPIO1_EN            0x00c70000      /* Set gpio output enable       */
 270 #define CONFIG_SYS_GPIO_OUT            0x00000008      /* Set outputs to default state */
 271 #define CONFIG_SYS_GPIO1_OUT           0x00c70000      /* Set outputs to default state */
 272
 273 #define CONFIG_SYS_GPIO1_LED           0x00400000      /* user led                     */
 274
 275 /*-----------------------------------------------------------------------
 276  * FPGA stuff
 277  */
 278 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now    */
 279 #define CONFIG_SYS_FPGA_MAX_SIZE        512*1024    /* 512kByte is enough for XC2S200*/
 280
 281 /* FPGA program pin configuration */
 282 #define CONFIG_SYS_FPGA_PRG             0x00010000  /* FPGA program pin (ppc output) */
 283 #define CONFIG_SYS_FPGA_CLK             0x00040000  /* FPGA clk pin (ppc output)     */
 284 #define CONFIG_SYS_FPGA_DATA            0x00020000  /* FPGA data pin (ppc output)    */
 285 #define CONFIG_SYS_FPGA_INIT            0x00080000  /* FPGA init pin (ppc input)     */
 286 #define CONFIG_SYS_FPGA_DONE            0x00100000  /* FPGA done pin (ppc input)     */
 287
 288 #endif  /* _TASREG_H */