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1 /*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2004-2006
6 * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29
30 /*
31 * High Level Configuration Options
32 * (easy to change)
33 */
34
35 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36 #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
37 #define CONFIG_TQM5200 1 /* ... on TQM5200 module */
38 #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
39
40 #ifndef CONFIG_CAM5200 /* On a Cameron board or ... */
41 #define CONFIG_STK52XX 1 /* ... on a STK52XX board */
42 #endif
43
44 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
45
46 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
47 #define BOOTFLAG_WARM 0x02 /* Software reboot */
48
49 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
50 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
51 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
52 #endif
53
54 /*
55 * Serial console configuration
56 */
57 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
58 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
59 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
60
61 #ifdef CONFIG_STK52XX
62 #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
63 #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
64 #define CONFIG_PS2SERIAL 6 /* .. on PSC6 */
65 #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
66 #define CONFIG_BOARD_EARLY_INIT_R
67 #endif /* CONFIG_STK52XX */
68
69 /*
70 * PCI Mapping:
71 * 0x40000000 - 0x4fffffff - PCI Memory
72 * 0x50000000 - 0x50ffffff - PCI IO Space
73 */
74 #ifdef CONFIG_STK52XX
75 #define CONFIG_PCI 1
76 #define CONFIG_PCI_PNP 1
77 /* #define CONFIG_PCI_SCAN_SHOW 1 */
78
79 #define CONFIG_PCI_MEM_BUS 0x40000000
80 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
81 #define CONFIG_PCI_MEM_SIZE 0x10000000
82
83 #define CONFIG_PCI_IO_BUS 0x50000000
84 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
85 #define CONFIG_PCI_IO_SIZE 0x01000000
86
87 #define CONFIG_NET_MULTI 1
88 #define CONFIG_EEPRO100 1
89 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
90 #define CONFIG_NS8382X 1
91 #endif /* CONFIG_STK52XX */
92
93 #ifdef CONFIG_PCI
94 #define ADD_PCI_CMD CFG_CMD_PCI
95 #else
96 #define ADD_PCI_CMD 0
97 #endif
98
99 /*
100 * Video console
101 */
102 #ifndef CONFIG_TQM5200S /* No graphics controller on TQM5200S */
103 #define CONFIG_VIDEO
104 #define CONFIG_VIDEO_SM501
105 #define CONFIG_VIDEO_SM501_32BPP
106 #define CONFIG_CFB_CONSOLE
107 #define CONFIG_VIDEO_LOGO
108 #define CONFIG_VGA_AS_SINGLE_DEVICE
109 #define CONFIG_CONSOLE_EXTRA_INFO
110 #define CONFIG_VIDEO_SW_CURSOR
111 #define CONFIG_SPLASH_SCREEN
112 #define CFG_CONSOLE_IS_IN_ENV
113 #endif
114
115 #ifdef CONFIG_VIDEO
116 #define ADD_BMP_CMD CFG_CMD_BMP
117 #else
118 #define ADD_BMP_CMD 0
119 #endif
120
121 /* Partitions */
122 #define CONFIG_MAC_PARTITION
123 #define CONFIG_DOS_PARTITION
124 #define CONFIG_ISO_PARTITION
125
126 /* USB */
127 #ifdef CONFIG_STK52XX
128 #define CONFIG_USB_OHCI
129 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
130 #define CONFIG_USB_STORAGE
131 #else
132 #define ADD_USB_CMD 0
133 #endif
134
135 #ifndef CONFIG_CAM5200
136 /* POST support */
137 #define CONFIG_POST (CFG_POST_MEMORY | \
138 CFG_POST_CPU | \
139 CFG_POST_I2C)
140 #endif
141
142 #ifdef CONFIG_POST
143 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
144 /* preserve space for the post_word at end of on-chip SRAM */
145 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
146 #else
147 #define CFG_CMD_POST_DIAG 0
148 #endif
149
150 /* IDE */
151 #if defined (CONFIG_MINIFAP) || defined (CONFIG_STK52XX)
152 #define ADD_IDE_CMD (CFG_CMD_IDE | CFG_CMD_FAT | CFG_CMD_EXT2)
153 #else
154 #define ADD_IDE_CMD 0
155 #endif
156
157 /*
158 * Supported commands
159 */
160 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
161 ADD_BMP_CMD | \
162 ADD_IDE_CMD | \
163 ADD_PCI_CMD | \
164 ADD_USB_CMD | \
165 CFG_CMD_ASKENV | \
166 CFG_CMD_DATE | \
167 CFG_CMD_DHCP | \
168 CFG_CMD_EEPROM | \
169 CFG_CMD_I2C | \
170 CFG_CMD_JFFS2 | \
171 CFG_CMD_MII | \
172 CFG_CMD_NFS | \
173 CFG_CMD_PING | \
174 CFG_CMD_POST_DIAG | \
175 CFG_CMD_REGINFO | \
176 CFG_CMD_SNTP | \
177 CFG_CMD_BSP)
178
179 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
180 #include <cmd_confdefs.h>
181
182 #define CONFIG_TIMESTAMP /* display image timestamps */
183
184 #if (TEXT_BASE != 0xFFF00000)
185 # define CFG_LOWBOOT 1 /* Boot low */
186 #endif
187
188 /*
189 * Autobooting
190 */
191 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
192
193 #define CONFIG_PREBOOT "echo;" \
194 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
195 "echo"
196
197 #undef CONFIG_BOOTARGS
198
199 #ifdef CONFIG_STK52XX
200 # if defined(CONFIG_TQM5200_B)
201 # if defined(CFG_LOWBOOT)
202 # define ENV_UPDT \
203 "update=protect off FC000000 FC07FFFF;" \
204 "erase FC000000 FC07FFFF;" \
205 "cp.b 200000 FC000000 ${filesize};" \
206 "protect on FC000000 FC07FFFF\0"
207 # else /* highboot */
208 # define ENV_UPDT \
209 "update=protect off FFF00000 FFF7FFFF;" \
210 "erase FFF00000 FFF7FFFF;" \
211 "cp.b 200000 FFF00000 ${filesize};" \
212 "protect on FFF00000 FFF7FFFF\0"
213 # endif /* CFG_LOWBOOT */
214 # else /* !CONFIG_TQM5200_B */
215 # define ENV_UPDT \
216 "update=protect off FC000000 FC05FFFF;" \
217 "erase FC000000 FC05FFFF;" \
218 "cp.b 200000 FC000000 ${filesize};" \
219 "protect on FC000000 FC05FFFF\0"
220 # endif /* CONFIG_TQM5200_B */
221 #elif defined (CONFIG_CAM5200)
222 # define ENV_UPDT \
223 "update=protect off FC000000 FC03FFFF;" \
224 "erase FC000000 FC03FFFF;" \
225 "cp.b 200000 FC000000 ${filesize};" \
226 "protect on FC000000 FC03FFFF\0"
227 #else
228 # error "Unknown Carrier Board"
229 #endif /* CONFIG_STK52XX */
230
231 #define CONFIG_EXTRA_ENV_SETTINGS \
232 "netdev=eth0\0" \
233 "rootpath=/opt/eldk/ppc_6xx\0" \
234 "ramargs=setenv bootargs root=/dev/ram rw\0" \
235 "nfsargs=setenv bootargs root=/dev/nfs rw " \
236 "nfsroot=${serverip}:${rootpath}\0" \
237 "addip=setenv bootargs ${bootargs} " \
238 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
239 ":${hostname}:${netdev}:off panic=1\0" \
240 "addcons=setenv bootargs ${bootargs} " \
241 "console=ttyS0,${baudrate}\0" \
242 "flash_self=run ramargs addip addcons;" \
243 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
244 "flash_nfs=run nfsargs addip addcons;" \
245 "bootm ${kernel_addr}\0" \
246 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
247 "bootm\0" \
248 "bootfile=/tftpboot/tqm5200/uImage\0" \
249 "u-boot=/tftpboot/tqm5200/u-boot.bin\0" \
250 "load=tftp 200000 ${u-boot}\0" \
251 ENV_UPDT \
252 ""
253
254 #define CONFIG_BOOTCOMMAND "run net_nfs"
255
256 /*
257 * IPB Bus clocking configuration.
258 */
259 #define CFG_IPBSPEED_133 /* define for 133MHz speed */
260
261 #if defined(CFG_IPBSPEED_133)
262 /*
263 * PCI Bus clocking configuration
264 *
265 * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
266 * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
267 * been tested with a IPB Bus Clock of 66 MHz.
268 */
269 #define CFG_PCISPEED_66 /* define for 66MHz speed */
270 #endif
271
272 /*
273 * I2C configuration
274 */
275 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
276 #ifdef CONFIG_TQM5200_REV100
277 #define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
278 #else
279 #define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
280 #endif
281
282 /*
283 * I2C clock frequency
284 *
285 * Please notice, that the resulting clock frequency could differ from the
286 * configured value. This is because the I2C clock is derived from system
287 * clock over a frequency divider with only a few divider values. U-boot
288 * calculates the best approximation for CFG_I2C_SPEED. However the calculated
289 * approximation allways lies below the configured value, never above.
290 */
291 #define CFG_I2C_SPEED 100000 /* 100 kHz */
292 #define CFG_I2C_SLAVE 0x7F
293
294 /*
295 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
296 * also). For other EEPROMs configuration should be verified. On Mini-FAP the
297 * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
298 * same configuration could be used.
299 */
300 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
301 #define CFG_I2C_EEPROM_ADDR_LEN 2
302 #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
303 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
304
305 /*
306 * HW-Monitor configuration on Mini-FAP
307 */
308 #if defined (CONFIG_MINIFAP)
309 #define CFG_I2C_HWMON_ADDR 0x2C
310 #endif
311
312 /* List of I2C addresses to be verified by POST */
313 #if defined (CONFIG_MINIFAP)
314 #undef I2C_ADDR_LIST
315 #define I2C_ADDR_LIST { CFG_I2C_EEPROM_ADDR, \
316 CFG_I2C_HWMON_ADDR, \
317 CFG_I2C_SLAVE }
318 #endif
319
320 /*
321 * Flash configuration
322 */
323 #define CFG_FLASH_BASE 0xFC000000
324
325 /* use CFI flash driver */
326 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
327 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
328 #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
329 #define CFG_FLASH_EMPTY_INFO
330 #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
331 #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
332 #define CFG_FLASH_USE_BUFFER_WRITE 1
333
334 #if defined (CONFIG_CAM5200)
335 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
336 #elif defined(CONFIG_TQM5200_B)
337 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00080000)
338 #else
339 # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
340 #endif
341
342 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
343 (= chip selects) */
344
345 /* Dynamic MTD partition support */
346 #define CONFIG_JFFS2_CMDLINE
347 #define MTDIDS_DEFAULT "nor0=TQM5200-0"
348
349 #ifdef CONFIG_STK52XX
350 # if defined(CONFIG_TQM5200_B)
351 # if defined(CFG_LOWBOOT)
352 # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:1m(firmware)," \
353 "1536k(kernel)," \
354 "3584k(small-fs)," \
355 "2m(initrd)," \
356 "8m(misc)," \
357 "16m(big-fs)"
358 # else /* highboot */
359 # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:2560k(kernel)," \
360 "3584k(small-fs)," \
361 "2m(initrd)," \
362 "8m(misc)," \
363 "15m(big-fs)," \
364 "1m(firmware)"
365 # endif /* CFG_LOWBOOT */
366 # else /* !CONFIG_TQM5200_B */
367 # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
368 "1408k(kernel)," \
369 "2m(initrd)," \
370 "4m(small-fs)," \
371 "8m(misc)," \
372 "16m(big-fs)"
373 # endif /* CONFIG_TQM5200_B */
374 #elif defined (CONFIG_CAM5200)
375 # define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:768k(firmware)," \
376 "1792k(kernel)," \
377 "3584k(small-fs)," \
378 "2m(initrd)," \
379 "8m(misc)," \
380 "16m(big-fs)"
381 #else
382 # error "Unknown Carrier Board"
383 #endif /* CONFIG_STK52XX */
384
385 /*
386 * Environment settings
387 */
388 #define CFG_ENV_IS_IN_FLASH 1
389 #define CFG_ENV_SIZE 0x4000 /* 16 k - keep small for fast booting */
390 #if defined(CONFIG_TQM5200_B)
391 #define CFG_ENV_SECT_SIZE 0x40000
392 #else
393 #define CFG_ENV_SECT_SIZE 0x20000
394 #endif /* CONFIG_TQM5200_B */
395 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
396 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
397
398 /*
399 * Memory map
400 */
401 #define CFG_MBAR 0xF0000000
402 #define CFG_SDRAM_BASE 0x00000000
403 #define CFG_DEFAULT_MBAR 0x80000000
404
405 /* Use ON-Chip SRAM until RAM will be available */
406 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
407 #ifdef CONFIG_POST
408 /* preserve space for the post_word at end of on-chip SRAM */
409 #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
410 #else
411 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
412 #endif
413
414
415 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
416 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
417 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
418
419 #define CFG_MONITOR_BASE TEXT_BASE
420 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
421 # define CFG_RAMBOOT 1
422 #endif
423
424 #if defined (CONFIG_CAM5200)
425 # define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
426 #elif defined(CONFIG_TQM5200_B)
427 # define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
428 #else
429 # define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
430 #endif
431
432 #define CFG_MALLOC_LEN (1024 << 10) /* Reserve 1024 kB for malloc() */
433 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
434
435 /*
436 * Ethernet configuration
437 */
438 #define CONFIG_MPC5xxx_FEC 1
439 /*
440 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
441 */
442 /* #define CONFIG_FEC_10MBIT 1 */
443 #define CONFIG_PHY_ADDR 0x00
444
445 /*
446 * GPIO configuration
447 *
448 * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
449 * Bit 0 (mask: 0x80000000): 1
450 * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
451 * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
452 * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
453 * Use for REV200 STK52XX boards. Do not use with REV100 modules
454 * (because, there I2C1 is used as I2C bus)
455 * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
456 * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
457 * 000 -> All PSC2 pins are GIOPs
458 * 001 -> CAN1/2 on PSC2 pins
459 * Use for REV100 STK52xx boards
460 * use PSC6:
461 * on STK52xx:
462 * use as UART. Pins PSC6_0 to PSC6_3 are used.
463 * Bits 9:11 (mask: 0x00700000):
464 * 101 -> PSC6 : Extended POST test is not available
465 * on MINI-FAP and TQM5200_IB:
466 * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
467 * 000 -> PSC6 could not be used as UART, CODEC or IrDA
468 * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
469 * tests.
470 */
471 #if defined (CONFIG_MINIFAP)
472 # define CFG_GPS_PORT_CONFIG 0x91000004
473 #elif defined (CONFIG_STK52XX)
474 # if defined (CONFIG_STK52XX_REV100)
475 # define CFG_GPS_PORT_CONFIG 0x81500014
476 # else /* STK52xx REV200 and above */
477 # if defined (CONFIG_TQM5200_REV100)
478 # error TQM5200 REV100 not supported on STK52XX REV200 or above
479 # else/* TQM5200 REV200 and above */
480 # define CFG_GPS_PORT_CONFIG 0x91500004
481 # endif
482 # endif
483 #else /* TMQ5200 Inbetriebnahme-Board */
484 # define CFG_GPS_PORT_CONFIG 0x81000004
485 #endif
486
487 /*
488 * RTC configuration
489 */
490 #if defined (CONFIG_STK52XX) && !defined (CONFIG_STK52XX_REV100)
491 # define CONFIG_RTC_M41T11 1
492 # define CFG_I2C_RTC_ADDR 0x68
493 # define CFG_M41T11_BASE_YEAR 1900 /* because Linux uses the same base
494 year */
495 #else
496 # define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
497 #endif
498
499 /*
500 * Miscellaneous configurable options
501 */
502 #define CFG_LONGHELP /* undef to save memory */
503 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
504
505 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
506 #define CFG_PROMPT_HUSH_PS2 "> "
507
508 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
509 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
510 #else
511 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
512 #endif
513 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
514 #define CFG_MAXARGS 16 /* max number of command args */
515 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
516
517 /* Enable an alternate, more extensive memory test */
518 #define CFG_ALT_MEMTEST
519
520 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
521 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
522
523 #define CFG_LOAD_ADDR 0x100000 /* default load address */
524
525 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
526
527 /*
528 * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
529 * which is normally part of the default commands (CFV_CMD_DFL)
530 */
531 #define CONFIG_LOOPW
532
533 /*
534 * Various low-level settings
535 */
536 #if defined(CONFIG_MPC5200)
537 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
538 #define CFG_HID0_FINAL HID0_ICE
539 #else
540 #define CFG_HID0_INIT 0
541 #define CFG_HID0_FINAL 0
542 #endif
543
544 #define CFG_BOOTCS_START CFG_FLASH_BASE
545 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
546 #ifdef CFG_PCISPEED_66
547 #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
548 #else
549 #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
550 #endif
551 #define CFG_CS0_START CFG_FLASH_BASE
552 #define CFG_CS0_SIZE CFG_FLASH_SIZE
553
554 #define CONFIG_LAST_STAGE_INIT
555
556 /*
557 * SRAM - Do not map below 2 GB in address space, because this area is used
558 * for SDRAM autosizing.
559 */
560 #define CFG_CS2_START 0xE5000000
561 #define CFG_CS2_SIZE 0x100000 /* 1 MByte */
562 #define CFG_CS2_CFG 0x0004D930
563
564 /*
565 * Grafic controller - Do not map below 2 GB in address space, because this
566 * area is used for SDRAM autosizing.
567 */
568 #define SM501_FB_BASE 0xE0000000
569 #define CFG_CS1_START (SM501_FB_BASE)
570 #define CFG_CS1_SIZE 0x4000000 /* 64 MByte */
571 #define CFG_CS1_CFG 0x8F48FF70
572 #define SM501_MMIO_BASE CFG_CS1_START + 0x03E00000
573
574 #define CFG_CS_BURST 0x00000000
575 #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
576
577 #define CFG_RESET_ADDRESS 0xff000000
578
579 /*-----------------------------------------------------------------------
580 * USB stuff
581 *-----------------------------------------------------------------------
582 */
583 #define CONFIG_USB_CLOCK 0x0001BBBB
584 #define CONFIG_USB_CONFIG 0x00001000
585
586 /*-----------------------------------------------------------------------
587 * IDE/ATA stuff Supports IDE harddisk
588 *-----------------------------------------------------------------------
589 */
590
591 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
592
593 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
594 #undef CONFIG_IDE_LED /* LED for ide not supported */
595
596 #define CONFIG_IDE_RESET /* reset for ide supported */
597 #define CONFIG_IDE_PREINIT
598
599 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
600 #define CFG_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
601
602 #define CFG_ATA_IDE0_OFFSET 0x0000
603
604 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
605
606 /* Offset for data I/O */
607 #define CFG_ATA_DATA_OFFSET (0x0060)
608
609 /* Offset for normal register accesses */
610 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
611
612 /* Offset for alternate registers */
613 #define CFG_ATA_ALT_OFFSET (0x005C)
614
615 /* Interval between registers */
616 #define CFG_ATA_STRIDE 4
617
618 #endif /* __CONFIG_H */