include/configs/TQM8260.h

   1 /*
   2  * (C) Copyright 2001-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * Imported from global configuration:
  33  *      CONFIG_MPC8255
  34  *      CONFIG_MPC8265
  35  *      CONFIG_200MHz
  36  *      CONFIG_266MHz
  37  *      CONFIG_300MHz
  38  *      CONFIG_L2_CACHE
  39  *      CONFIG_BUSMODE_60x
  40  */
  41
  42 /*
  43  * High Level Configuration Options
  44  * (easy to change)
  45  */
  46
  47 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  48
  49 #if 0
  50 #define CONFIG_TQM8260          100     /* ...on a TQM8260 module Rev.100       */
  51 #else
  52 #define CONFIG_TQM8260          200     /* ...on a TQM8260 module Rev.200       */
  53 #endif
  54
  55 #define CONFIG_CPM2             1       /* Has a CPM2 */
  56
  57 #define CONFIG_82xx_CONS_SMC1   1       /* console on SMC1                      */
  58
  59 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  60
  61 #define CONFIG_BOOTCOUNT_LIMIT
  62
  63 #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  64 #define CONFIG_BAUDRATE         230400
  65 #else
  66 #define CONFIG_BAUDRATE         9600
  67 #endif
  68
  69 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  70
  71 #undef  CONFIG_BOOTARGS
  72
  73 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  74         "netdev=eth0\0"                                                 \
  75         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  76                 "nfsroot=${serverip}:${rootpath}\0"                     \
  77         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  78         "addip=setenv bootargs ${bootargs} "                            \
  79                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  80                 ":${hostname}:${netdev}:off panic=1\0"                  \
  81         "flash_nfs=run nfsargs addip;"                                  \
  82                 "bootm ${kernel_addr}\0"                                \
  83         "flash_self=run ramargs addip;"                                 \
  84                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  85         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  86         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  87         "bootfile=/tftpboot/TQM8260/uImage\0"                           \
  88         "kernel_addr=40040000\0"                                        \
  89         "ramdisk_addr=40100000\0"                                       \
  90         ""
  91 #define CONFIG_BOOTCOMMAND      "run flash_self"
  92
  93 /* enable I2C and select the hardware/software driver */
  94 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  95 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  96 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
  97 #define CONFIG_SYS_I2C_SLAVE            0x7F
  98
  99 /*
 100  * Software (bit-bang) I2C driver configuration
 101  */
 102
 103 /* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
 104 #if (CONFIG_TQM8260 <= 100)
 105
 106 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 107 #define I2C_ACTIVE      (iop->pdir |=  0x00020000)
 108 #define I2C_TRISTATE    (iop->pdir &= ~0x00020000)
 109 #define I2C_READ        ((iop->pdat & 0x00020000) != 0)
 110 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00020000; \
 111                         else    iop->pdat &= ~0x00020000
 112 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00010000; \
 113                         else    iop->pdat &= ~0x00010000
 114 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 115
 116 #else
 117
 118 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 119 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 120 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 121 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 122 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 123                         else    iop->pdat &= ~0x00010000
 124 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 125                         else    iop->pdat &= ~0x00020000
 126 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 127 #endif
 128
 129 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 130 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 131 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 132 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 133
 134 #define CONFIG_I2C_X
 135
 136 /*
 137  * select serial console configuration
 138  *
 139  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 140  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 141  * for SCC).
 142  *
 143  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 144  * defined elsewhere (for example, on the cogent platform, there are serial
 145  * ports on the motherboard which are used for the serial console - see
 146  * cogent/cma101/serial.[ch]).
 147  */
 148 #define CONFIG_CONS_ON_SMC              /* define if console on SMC */
 149 #undef  CONFIG_CONS_ON_SCC              /* define if console on SCC */
 150 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
 151 #ifdef CONFIG_82xx_CONS_SMC1
 152 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
 153 #endif
 154 #ifdef CONFIG_82xx_CONS_SMC2
 155 #define CONFIG_CONS_INDEX       2       /* which serial channel for console */
 156 #endif
 157
 158 #undef  CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 159 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
 160 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9 */
 161
 162 /*
 163  * select ethernet configuration
 164  *
 165  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 166  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 167  * for FCC)
 168  *
 169  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 170  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 171  *
 172  * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
 173  * X.29 connector, and FCC2 is hardwired to the X.1 connector)
 174  */
 175 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 176 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 177 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 178 #define CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
 179
 180 #if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
 181
 182 /*
 183  *  - RX clk is CLK11
 184  *  - TX clk is CLK12
 185  */
 186 # define CONFIG_SYS_CMXSCR_VALUE        (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
 187
 188 #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
 189
 190 /*
 191  * - Rx-CLK is CLK13
 192  * - Tx-CLK is CLK14
 193  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 194  * - Enable Full Duplex in FSMR
 195  */
 196 # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 197 # define CONFIG_SYS_CMXFCR_VALUE        (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 198 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 199 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 200
 201 #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
 202
 203
 204 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 205 #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
 206 #  define CONFIG_8260_CLKIN     66666666        /* in Hz */
 207 #else   /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
 208 # ifndef CONFIG_300MHz
 209 #  define CONFIG_8260_CLKIN     66666666        /* in Hz */
 210 # else
 211 #  define CONFIG_8260_CLKIN     83333000        /* in Hz */
 212 # endif
 213 #endif  /* CONFIG_MPC8255 */
 214
 215 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 216 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 217
 218 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 219
 220 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 221
 222
 223 /*
 224  * BOOTP options
 225  */
 226 #define CONFIG_BOOTP_SUBNETMASK
 227 #define CONFIG_BOOTP_GATEWAY
 228 #define CONFIG_BOOTP_HOSTNAME
 229 #define CONFIG_BOOTP_BOOTPATH
 230 #define CONFIG_BOOTP_BOOTFILESIZE
 231
 232
 233 /*
 234  * Command line configuration.
 235  */
 236 #include <config_cmd_default.h>
 237
 238 #define CONFIG_CMD_DHCP
 239 #define CONFIG_CMD_I2C
 240 #define CONFIG_CMD_EEPROM
 241 #define CONFIG_CMD_NFS
 242 #define CONFIG_CMD_SNTP
 243
 244
 245 /*
 246  * Miscellaneous configurable options
 247  */
 248 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 249 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 250
 251 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 252 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 253 #ifdef  CONFIG_SYS_HUSH_PARSER
 254 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 255 #endif
 256
 257 #if defined(CONFIG_CMD_KGDB)
 258 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 259 #else
 260 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 261 #endif
 262 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 263 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 264 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 265
 266 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 267 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 268
 269 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 270
 271 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 272
 273 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 274
 275 #define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC     /* "bad" address                */
 276
 277 /*
 278  * For booting Linux, the board info and command line data
 279  * have to be in the first 8 MB of memory, since this is
 280  * the maximum mapped by the Linux kernel during initialization.
 281  */
 282 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 283
 284
 285 /* What should the base address of the main FLASH be and how big is
 286  * it (in MBytes)? This must contain TEXT_BASE from board/tqm8260/config.mk
 287  * The main FLASH is whichever is connected to *CS0.
 288  */
 289 #define CONFIG_SYS_FLASH0_BASE 0x40000000
 290 #define CONFIG_SYS_FLASH1_BASE 0x60000000
 291 #define CONFIG_SYS_FLASH0_SIZE 32
 292 #define CONFIG_SYS_FLASH1_SIZE 32
 293
 294 /* Flash bank size (for preliminary settings)
 295  */
 296 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 297
 298 /*-----------------------------------------------------------------------
 299  * FLASH organization
 300  */
 301 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 302 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 303
 304 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 305 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 306
 307 #if 0
 308 /* Start port with environment in flash; switch to EEPROM later */
 309 #define CONFIG_ENV_IS_IN_FLASH  1
 310 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE+0x40000)
 311 #define CONFIG_ENV_SIZE         0x40000
 312 #define CONFIG_ENV_SECT_SIZE    0x40000
 313 #else
 314 /* Final version: environment in EEPROM */
 315 #define CONFIG_ENV_IS_IN_EEPROM 1
 316 #define CONFIG_ENV_OFFSET               0
 317 #define CONFIG_ENV_SIZE         2048
 318 #endif
 319
 320 /*-----------------------------------------------------------------------
 321  * Hardware Information Block
 322  */
 323 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 324 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 325 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 326
 327 /*-----------------------------------------------------------------------
 328  * Hard Reset Configuration Words
 329  *
 330  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 331  * defines for the various registers affected by the HRCW e.g. changing
 332  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 333  */
 334 #define __HRCW__ALL__           (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
 335
 336 #if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
 337 #  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__ | HRCW_MODCK_H0111)
 338 #else   /* ! MPC8255 && !MPC8265 */
 339 # if defined(CONFIG_266MHz)
 340 #  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__ | HRCW_MODCK_H0111)
 341 # elif defined(CONFIG_300MHz)
 342 #  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__ | HRCW_MODCK_H0110)
 343 # else
 344 #  define CONFIG_SYS_HRCW_MASTER        (__HRCW__ALL__)
 345 # endif
 346 #endif  /* CONFIG_MPC8255 */
 347
 348 /* no slaves so just fill with zeros */
 349 #define CONFIG_SYS_HRCW_SLAVE1          0
 350 #define CONFIG_SYS_HRCW_SLAVE2          0
 351 #define CONFIG_SYS_HRCW_SLAVE3          0
 352 #define CONFIG_SYS_HRCW_SLAVE4          0
 353 #define CONFIG_SYS_HRCW_SLAVE5          0
 354 #define CONFIG_SYS_HRCW_SLAVE6          0
 355 #define CONFIG_SYS_HRCW_SLAVE7          0
 356
 357 /*-----------------------------------------------------------------------
 358  * Internal Memory Mapped Register
 359  */
 360 #define CONFIG_SYS_IMMR         0xFFF00000
 361
 362 /*-----------------------------------------------------------------------
 363  * Definitions for initial stack pointer and data area (in DPRAM)
 364  */
 365 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 366 #define CONFIG_SYS_INIT_RAM_END 0x4000  /* End of used area in DPRAM    */
 367 #define CONFIG_SYS_GBL_DATA_SIZE        128 /* size in bytes reserved for initial data*/
 368 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 369 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 370
 371 /*-----------------------------------------------------------------------
 372  * Start addresses for the final memory configuration
 373  * (Set up by the startup code)
 374  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 375  *
 376  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
 377  * is mapped at SDRAM_BASE2_PRELIM.
 378  */
 379 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 380 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH0_BASE
 381 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 382 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 383 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 384
 385 /*
 386  * Internal Definitions
 387  *
 388  * Boot Flags
 389  */
 390 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 391 #define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 392
 393
 394 /*-----------------------------------------------------------------------
 395  * Cache Configuration
 396  */
 397 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 398 #if defined(CONFIG_CMD_KGDB)
 399 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 400 #endif
 401
 402 /*-----------------------------------------------------------------------
 403  * HIDx - Hardware Implementation-dependent Registers                    2-11
 404  *-----------------------------------------------------------------------
 405  * HID0 also contains cache control - initially enable both caches and
 406  * invalidate contents, then the final state leaves only the instruction
 407  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 408  * but Soft reset does not.
 409  *
 410  * HID1 has only read-only information - nothing to set.
 411  */
 412 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 413                                 HID0_IFEM|HID0_ABE)
 414 #define CONFIG_SYS_HID0_FINAL  (HID0_IFEM|HID0_ABE)
 415 #define CONFIG_SYS_HID2        0
 416
 417 /*-----------------------------------------------------------------------
 418  * RMR - Reset Mode Register                                     5-5
 419  *-----------------------------------------------------------------------
 420  * turn on Checkstop Reset Enable
 421  */
 422 #define CONFIG_SYS_RMR         RMR_CSRE
 423
 424 /*-----------------------------------------------------------------------
 425  * BCR - Bus Configuration                                       4-25
 426  *-----------------------------------------------------------------------
 427  */
 428 #ifdef  CONFIG_BUSMODE_60x
 429 #define CONFIG_SYS_BCR         (BCR_EBM|BCR_L2C|BCR_LETM|\
 430                          BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode  */
 431 #else
 432 #define BCR_APD01       0x10000000
 433 #define CONFIG_SYS_BCR          (BCR_APD01|BCR_ETM|BCR_LETM)    /* 8260 mode */
 434 #endif
 435
 436 /*-----------------------------------------------------------------------
 437  * SIUMCR - SIU Module Configuration                             4-31
 438  *-----------------------------------------------------------------------
 439  */
 440 #if 0
 441 #define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC10|SIUMCR_APPC10)
 442 #else
 443 #define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10)
 444 #endif
 445
 446
 447 /*-----------------------------------------------------------------------
 448  * SYPCR - System Protection Control                             4-35
 449  * SYPCR can only be written once after reset!
 450  *-----------------------------------------------------------------------
 451  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 452  */
 453 #if defined(CONFIG_WATCHDOG)
 454 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 455                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 456 #else
 457 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 458                          SYPCR_SWRI|SYPCR_SWP)
 459 #endif /* CONFIG_WATCHDOG */
 460
 461 /*-----------------------------------------------------------------------
 462  * TMCNTSC - Time Counter Status and Control                     4-40
 463  *-----------------------------------------------------------------------
 464  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 465  * and enable Time Counter
 466  */
 467 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 468
 469 /*-----------------------------------------------------------------------
 470  * PISCR - Periodic Interrupt Status and Control                 4-42
 471  *-----------------------------------------------------------------------
 472  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 473  * Periodic timer
 474  */
 475 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 476
 477 /*-----------------------------------------------------------------------
 478  * SCCR - System Clock Control                                   9-8
 479  *-----------------------------------------------------------------------
 480  * Ensure DFBRG is Divide by 16
 481  */
 482 #define CONFIG_SYS_SCCR        0
 483
 484 /*-----------------------------------------------------------------------
 485  * RCCR - RISC Controller Configuration                         13-7
 486  *-----------------------------------------------------------------------
 487  */
 488 #define CONFIG_SYS_RCCR        0
 489
 490 /*
 491  * Init Memory Controller:
 492  *
 493  * Bank Bus     Machine PortSz  Device
 494  * ---- ---     ------- ------  ------
 495  *  0   60x     GPCM    64 bit  FLASH
 496  *  1   60x     SDRAM   64 bit  SDRAM
 497  *  2   Local   SDRAM   32 bit  SDRAM
 498  *
 499  */
 500
 501         /* Initialize SDRAM on local bus
 502          */
 503 #define CONFIG_SYS_INIT_LOCAL_SDRAM
 504
 505 #define SDRAM_MAX_SIZE  0x08000000      /* max. 128 MB          */
 506
 507 /* Minimum mask to separate preliminary
 508  * address ranges for CS[0:2]
 509  */
 510 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (512<<20)       /* less than 512 MB */
 511 #define CONFIG_SYS_LOCAL_SDRAM_LIMIT    (128<<20)       /* less than 128 MB */
 512
 513 #define CONFIG_SYS_MPTPR       0x4000
 514
 515 /*-----------------------------------------------------------------------------
 516  * Address for Mode Register Set (MRS) command
 517  *-----------------------------------------------------------------------------
 518  * In fact, the address is rather configuration data presented to the SDRAM on
 519  * its address lines. Because the address lines may be mux'ed externally either
 520  * for 8 column or 9 column devices, some bits appear twice in the 8260's
 521  * address:
 522  *
 523  * |   (RFU)   |   (RFU)   | WBL |    TM    |     CL    |  BT | Burst Length |
 524  * | BA1   BA0 | A12 : A10 |  A9 |  A8   A7 |  A6 : A4  |  A3 |   A2 :  A0   |
 525  *  8 columns mux'ing:     |  A9 | A10  A21 | A22 : A24 | A25 |  A26 : A28   |
 526  *  9 columns mux'ing:     |  A8 | A20  A21 | A22 : A24 | A25 |  A26 : A28   |
 527  *  Settings:              |  0  |  0    0  |  0  1  0  |  0  |   0  1  0    |
 528  *-----------------------------------------------------------------------------
 529  */
 530 #define CONFIG_SYS_MRS_OFFS     0x00000110
 531
 532
 533 /* Bank 0 - FLASH
 534  */
 535 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 536                          BRx_PS_64                      |\
 537                          BRx_MS_GPCM_P                  |\
 538                          BRx_V)
 539
 540 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 541                          ORxG_CSNT                      |\
 542                          ORxG_ACS_DIV1                  |\
 543                          ORxG_SCY_3_CLK                 |\
 544                          ORxG_EHTR                      |\
 545                          ORxG_TRLX)
 546
 547         /* SDRAM on TQM8260 can have either 8 or 9 columns.
 548          * The number affects configuration values.
 549          */
 550
 551 /* Bank 1 - 60x bus SDRAM
 552  */
 553 #define CONFIG_SYS_PSRT        0x20
 554 #define CONFIG_SYS_LSRT        0x20
 555 #ifndef CONFIG_SYS_RAMBOOT
 556 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 557                          BRx_PS_64                      |\
 558                          BRx_MS_SDRAM_P                 |\
 559                          BRx_V)
 560
 561 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1_8COL
 562
 563
 564         /* SDRAM initialization values for 8-column chips
 565          */
 566 #define CONFIG_SYS_OR1_8COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 567                          ORxS_BPD_4                     |\
 568                          ORxS_ROWST_PBI1_A7             |\
 569                          ORxS_NUMR_12)
 570
 571 #define CONFIG_SYS_PSDMR_8COL  (PSDMR_PBI                      |\
 572                          PSDMR_SDAM_A15_IS_A5           |\
 573                          PSDMR_BSMA_A12_A14             |\
 574                          PSDMR_SDA10_PBI1_A8            |\
 575                          PSDMR_RFRC_7_CLK               |\
 576                          PSDMR_PRETOACT_2W              |\
 577                          PSDMR_ACTTORW_2W               |\
 578                          PSDMR_LDOTOPRE_1C              |\
 579                          PSDMR_WRC_2C                   |\
 580                          PSDMR_EAMUX                    |\
 581                          PSDMR_CL_2)
 582
 583         /* SDRAM initialization values for 9-column chips
 584          */
 585 #define CONFIG_SYS_OR1_9COL    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 586                          ORxS_BPD_4                     |\
 587                          ORxS_ROWST_PBI1_A5             |\
 588                          ORxS_NUMR_13)
 589
 590 #define CONFIG_SYS_PSDMR_9COL  (PSDMR_PBI                      |\
 591                          PSDMR_SDAM_A16_IS_A5           |\
 592                          PSDMR_BSMA_A12_A14             |\
 593                          PSDMR_SDA10_PBI1_A7            |\
 594                          PSDMR_RFRC_7_CLK               |\
 595                          PSDMR_PRETOACT_2W              |\
 596                          PSDMR_ACTTORW_2W               |\
 597                          PSDMR_LDOTOPRE_1C              |\
 598                          PSDMR_WRC_2C                   |\
 599                          PSDMR_EAMUX                    |\
 600                          PSDMR_CL_2)
 601
 602 /* Bank 2 - Local bus SDRAM
 603  */
 604 #ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
 605 #define CONFIG_SYS_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
 606                          BRx_PS_32                      |\
 607                          BRx_MS_SDRAM_L                 |\
 608                          BRx_V)
 609
 610 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_OR2_8COL
 611
 612 #define SDRAM_BASE2_PRELIM      0x80000000
 613
 614         /* SDRAM initialization values for 8-column chips
 615          */
 616 #define CONFIG_SYS_OR2_8COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 617                          ORxS_BPD_4                     |\
 618                          ORxS_ROWST_PBI1_A8             |\
 619                          ORxS_NUMR_12)
 620
 621 #define CONFIG_SYS_LSDMR_8COL  (PSDMR_PBI                      |\
 622                          PSDMR_SDAM_A15_IS_A5           |\
 623                          PSDMR_BSMA_A13_A15             |\
 624                          PSDMR_SDA10_PBI1_A9            |\
 625                          PSDMR_RFRC_7_CLK               |\
 626                          PSDMR_PRETOACT_2W              |\
 627                          PSDMR_ACTTORW_2W               |\
 628                          PSDMR_BL                       |\
 629                          PSDMR_LDOTOPRE_1C              |\
 630                          PSDMR_WRC_2C                   |\
 631                          PSDMR_CL_2)
 632
 633         /* SDRAM initialization values for 9-column chips
 634          */
 635 #define CONFIG_SYS_OR2_9COL    ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 636                          ORxS_BPD_4                     |\
 637                          ORxS_ROWST_PBI1_A6             |\
 638                          ORxS_NUMR_13)
 639
 640 #define CONFIG_SYS_LSDMR_9COL  (PSDMR_PBI                      |\
 641                          PSDMR_SDAM_A16_IS_A5           |\
 642                          PSDMR_BSMA_A13_A15             |\
 643                          PSDMR_SDA10_PBI1_A8            |\
 644                          PSDMR_RFRC_7_CLK               |\
 645                          PSDMR_PRETOACT_2W              |\
 646                          PSDMR_ACTTORW_2W               |\
 647                          PSDMR_BL                       |\
 648                          PSDMR_LDOTOPRE_1C              |\
 649                          PSDMR_WRC_2C                   |\
 650                          PSDMR_CL_2)
 651
 652 #endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
 653
 654 #endif /* CONFIG_SYS_RAMBOOT */
 655
 656 #endif  /* __CONFIG_H */