include/configs/TQM862L.h

   1 /*
   2  * (C) Copyright 2000-2014
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC860           1
  21 #define CONFIG_MPC860T          1
  22 #define CONFIG_MPC862           1
  23 #define CONFIG_DISPLAY_BOARDINFO
  24
  25 #define CONFIG_TQM862L          1       /* ...on a TQM8xxL module       */
  26
  27 #define CONFIG_SYS_TEXT_BASE    0x40000000
  28
  29 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  30 #define CONFIG_SYS_SMC_RXBUFLEN 128
  31 #define CONFIG_SYS_MAXIDLE      10
  32 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  33
  34 #define CONFIG_BOOTCOUNT_LIMIT
  35
  36 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  37
  38 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  39
  40 #define CONFIG_PREBOOT  "echo;" \
  41         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  42         "echo"
  43
  44 #undef  CONFIG_BOOTARGS
  45
  46 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  47         "netdev=eth0\0"                                                 \
  48         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  49                 "nfsroot=${serverip}:${rootpath}\0"                     \
  50         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  51         "addip=setenv bootargs ${bootargs} "                            \
  52                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  53                 ":${hostname}:${netdev}:off panic=1\0"                  \
  54         "flash_nfs=run nfsargs addip;"                                  \
  55                 "bootm ${kernel_addr}\0"                                \
  56         "flash_self=run ramargs addip;"                                 \
  57                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  58         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  59         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  60         "hostname=TQM862L\0"                                            \
  61         "bootfile=TQM862L/uImage\0"                                     \
  62         "fdt_addr=40040000\0"                                           \
  63         "kernel_addr=40060000\0"                                        \
  64         "ramdisk_addr=40200000\0"                                       \
  65         "u-boot=TQM862L/u-image.bin\0"                                  \
  66         "load=tftp 200000 ${u-boot}\0"                                  \
  67         "update=prot off 40000000 +${filesize};"                        \
  68                 "era 40000000 +${filesize};"                            \
  69                 "cp.b 200000 40000000 ${filesize};"                     \
  70                 "sete filesize;save\0"                                  \
  71         ""
  72 #define CONFIG_BOOTCOMMAND      "run flash_self"
  73
  74 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  75 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  76
  77 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  78
  79 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  80
  81 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  82
  83 /*
  84  * BOOTP options
  85  */
  86 #define CONFIG_BOOTP_SUBNETMASK
  87 #define CONFIG_BOOTP_GATEWAY
  88 #define CONFIG_BOOTP_HOSTNAME
  89 #define CONFIG_BOOTP_BOOTPATH
  90 #define CONFIG_BOOTP_BOOTFILESIZE
  91
  92 #define CONFIG_MAC_PARTITION
  93 #define CONFIG_DOS_PARTITION
  94
  95 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  96
  97 /*
  98  * Command line configuration.
  99  */
 100 #define CONFIG_CMD_DATE
 101 #define CONFIG_CMD_IDE
 102 #define CONFIG_CMD_JFFS2
 103
 104 #define CONFIG_NETCONSOLE
 105
 106 /*
 107  * Miscellaneous configurable options
 108  */
 109 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 110
 111 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 112
 113 #if defined(CONFIG_CMD_KGDB)
 114 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 115 #else
 116 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 117 #endif
 118 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 119 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 120 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 121
 122 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 123 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 124
 125 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 126
 127 /*
 128  * Low Level Configuration Settings
 129  * (address mappings, register initial values, etc.)
 130  * You should know what you are doing if you make changes here.
 131  */
 132 /*-----------------------------------------------------------------------
 133  * Internal Memory Mapped Register
 134  */
 135 #define CONFIG_SYS_IMMR         0xFFF00000
 136
 137 /*-----------------------------------------------------------------------
 138  * Definitions for initial stack pointer and data area (in DPRAM)
 139  */
 140 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 141 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 142 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 143 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 144
 145 /*-----------------------------------------------------------------------
 146  * Start addresses for the final memory configuration
 147  * (Set up by the startup code)
 148  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 149  */
 150 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 151 #define CONFIG_SYS_FLASH_BASE           0x40000000
 152 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 153 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 154 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 155
 156 /*
 157  * For booting Linux, the board info and command line data
 158  * have to be in the first 8 MB of memory, since this is
 159  * the maximum mapped by the Linux kernel during initialization.
 160  */
 161 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 162
 163 /*-----------------------------------------------------------------------
 164  * FLASH organization
 165  */
 166
 167 /* use CFI flash driver */
 168 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 169 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 170 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
 171 #define CONFIG_SYS_FLASH_EMPTY_INFO
 172 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 173 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks */
 174 #define CONFIG_SYS_MAX_FLASH_SECT       71      /* max number of sectors on one chip */
 175
 176 #define CONFIG_ENV_IS_IN_FLASH  1
 177 #define CONFIG_ENV_OFFSET               0x8000  /*   Offset   of Environment Sector     */
 178 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 179
 180 /* Address and size of Redundant Environment Sector     */
 181 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
 182 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 183
 184 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 185
 186 #define CONFIG_MISC_INIT_R              /* Make sure to remap flashes correctly */
 187
 188 /*-----------------------------------------------------------------------
 189  * Dynamic MTD partition support
 190  */
 191 #define CONFIG_CMD_MTDPARTS
 192 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 193 #define CONFIG_FLASH_CFI_MTD
 194 #define MTDIDS_DEFAULT          "nor0=TQM8xxL-0"
 195
 196 #define MTDPARTS_DEFAULT        "mtdparts=TQM8xxL-0:256k(u-boot),"      \
 197                                                 "128k(dtb),"            \
 198                                                 "1664k(kernel),"        \
 199                                                 "2m(rootfs),"           \
 200                                                 "4m(data)"
 201
 202 /*-----------------------------------------------------------------------
 203  * Hardware Information Block
 204  */
 205 #define CONFIG_SYS_HWINFO_OFFSET        0x0003FFC0      /* offset of HW Info block */
 206 #define CONFIG_SYS_HWINFO_SIZE          0x00000040      /* size   of HW Info block */
 207 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38      /* 'TQM8' */
 208
 209 /*-----------------------------------------------------------------------
 210  * Cache Configuration
 211  */
 212 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 213 #if defined(CONFIG_CMD_KGDB)
 214 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 215 #endif
 216
 217 /*-----------------------------------------------------------------------
 218  * SYPCR - System Protection Control                            11-9
 219  * SYPCR can only be written once after reset!
 220  *-----------------------------------------------------------------------
 221  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 222  */
 223 #if defined(CONFIG_WATCHDOG)
 224 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 225                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 226 #else
 227 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 228 #endif
 229
 230 /*-----------------------------------------------------------------------
 231  * SIUMCR - SIU Module Configuration                            11-6
 232  *-----------------------------------------------------------------------
 233  * PCMCIA config., multi-function pin tri-state
 234  */
 235 #ifndef CONFIG_CAN_DRIVER
 236 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 237 #else   /* we must activate GPL5 in the SIUMCR for CAN */
 238 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 239 #endif  /* CONFIG_CAN_DRIVER */
 240
 241 /*-----------------------------------------------------------------------
 242  * TBSCR - Time Base Status and Control                         11-26
 243  *-----------------------------------------------------------------------
 244  * Clear Reference Interrupt Status, Timebase freezing enabled
 245  */
 246 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 247
 248 /*-----------------------------------------------------------------------
 249  * RTCSC - Real-Time Clock Status and Control Register          11-27
 250  *-----------------------------------------------------------------------
 251  */
 252 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 253
 254 /*-----------------------------------------------------------------------
 255  * PISCR - Periodic Interrupt Status and Control                11-31
 256  *-----------------------------------------------------------------------
 257  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 258  */
 259 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 260
 261 /*-----------------------------------------------------------------------
 262  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 263  *-----------------------------------------------------------------------
 264  * Reset PLL lock status sticky bit, timer expired status bit and timer
 265  * interrupt status bit
 266  */
 267 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 268
 269 /*-----------------------------------------------------------------------
 270  * SCCR - System Clock and reset Control Register               15-27
 271  *-----------------------------------------------------------------------
 272  * Set clock output, timebase and RTC source and divider,
 273  * power management and some other internal clocks
 274  */
 275 #define SCCR_MASK       SCCR_EBDF11
 276 #define CONFIG_SYS_SCCR (SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 277                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 278                          SCCR_DFALCD00)
 279
 280 /*-----------------------------------------------------------------------
 281  * PCMCIA stuff
 282  *-----------------------------------------------------------------------
 283  *
 284  */
 285 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 286 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 287 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 288 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 289 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 290 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 291 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 292 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 293
 294 /*-----------------------------------------------------------------------
 295  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 296  *-----------------------------------------------------------------------
 297  */
 298
 299 #define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 300 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 301
 302 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 303 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 304 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 305
 306 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 307 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 308
 309 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 310
 311 #define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 312
 313 /* Offset for data I/O                  */
 314 #define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 315
 316 /* Offset for normal register accesses  */
 317 #define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 318
 319 /* Offset for alternate registers       */
 320 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 321
 322 /*-----------------------------------------------------------------------
 323  *
 324  *-----------------------------------------------------------------------
 325  *
 326  */
 327 #define CONFIG_SYS_DER  0
 328
 329 /*
 330  * Init Memory Controller:
 331  *
 332  * BR0/1 and OR0/1 (FLASH)
 333  */
 334
 335 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 336 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #1        */
 337
 338 /* used to re-map FLASH both when starting from SRAM or FLASH:
 339  * restrict access enough to keep SRAM working (if any)
 340  * but not too much to meddle with FLASH accesses
 341  */
 342 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 343 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 344
 345 /*
 346  * FLASH timing:
 347  */
 348 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 349                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 350
 351 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 352 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 353 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 354
 355 #define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 356 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 357 #define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 358
 359 /*
 360  * BR2/3 and OR2/3 (SDRAM)
 361  *
 362  */
 363 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 364 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 365 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 366
 367 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 368 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 369
 370 #define CONFIG_SYS_OR2_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
 371 #define CONFIG_SYS_BR2_PRELIM   ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 372
 373 #ifndef CONFIG_CAN_DRIVER
 374 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR2_PRELIM
 375 #define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 376 #else   /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
 377 #define CONFIG_SYS_CAN_BASE             0xC0000000      /* CAN mapped at 0xC0000000     */
 378 #define CONFIG_SYS_CAN_OR_AM            0xFFFF8000      /* 32 kB address mask           */
 379 #define CONFIG_SYS_OR3_CAN              (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
 380 #define CONFIG_SYS_BR3_CAN              ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
 381                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 382 #endif  /* CONFIG_CAN_DRIVER */
 383
 384 /*
 385  * Memory Periodic Timer Prescaler
 386  *
 387  * The Divider for PTA (refresh timer) configuration is based on an
 388  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 389  * the number of chip selects (NCS) and the actually needed refresh
 390  * rate is done by setting MPTPR.
 391  *
 392  * PTA is calculated from
 393  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 394  *
 395  *      gclk      CPU clock (not bus clock!)
 396  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 397  *
 398  * 4096  Rows from SDRAM example configuration
 399  * 1000  factor s -> ms
 400  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 401  *    4  Number of refresh cycles per period
 402  *   64  Refresh cycle in ms per number of rows
 403  * --------------------------------------------
 404  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 405  *
 406  *  50 MHz =>  50.000.000 / Divider =  98
 407  *  66 Mhz =>  66.000.000 / Divider = 129
 408  *  80 Mhz =>  80.000.000 / Divider = 156
 409  * 100 Mhz => 100.000.000 / Divider = 195
 410  */
 411
 412 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 32 * 1000) / (4 * 64))
 413 #define CONFIG_SYS_MAMR_PTA     98
 414
 415 /*
 416  * For 16 MBit, refresh rates could be 31.3 us
 417  * (= 64 ms / 2K = 125 / quad bursts).
 418  * For a simpler initialization, 15.6 us is used instead.
 419  *
 420  * #define CONFIG_SYS_MPTPR_2BK_2K      MPTPR_PTP_DIV32         for 2 banks
 421  * #define CONFIG_SYS_MPTPR_1BK_2K      MPTPR_PTP_DIV64         for 1 bank
 422  */
 423 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16         /* setting for 2 banks  */
 424 #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32         /* setting for 1 bank   */
 425
 426 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 427 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8          /* setting for 2 banks  */
 428 #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16         /* setting for 1 bank   */
 429
 430 /*
 431  * MAMR settings for SDRAM
 432  */
 433
 434 /* 8 column SDRAM */
 435 #define CONFIG_SYS_MAMR_8COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 436                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 437                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 438 /* 9 column SDRAM */
 439 #define CONFIG_SYS_MAMR_9COL    ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 440                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 441                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 442
 443 #define CONFIG_SCC1_ENET
 444 #define CONFIG_FEC_ENET
 445 #define CONFIG_ETHPRIME         "SCC"
 446
 447 #define CONFIG_HWCONFIG         1
 448
 449 #endif  /* __CONFIG_H */