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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / include / configs / TQM866M.h
1 /*
2 * (C) Copyright 2000-2008
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * board/config.h - configuration options, board specific
26 */
27
28 #ifndef __CONFIG_H
29 #define __CONFIG_H
30
31 /*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36 #define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37 #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
38
39 #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
40 #define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
41 #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
42 #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
43 /* (it will be used if there is no */
44 /* 'cpuclk' variable with valid value) */
45
46 #undef CONFIG_SYS_MEASURE_CPUCLK /* Measure real cpu clock */
47 /* (function measure_gclk() */
48 /* will be called) */
49 #ifdef CONFIG_SYS_MEASURE_CPUCLK
50 #define CONFIG_SYS_8XX_XIN 10000000 /* measure_gclk() needs this */
51 #endif
52
53 #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
54
55 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
56
57 #define CONFIG_BOOTCOUNT_LIMIT
58
59 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
60
61 #define CONFIG_BOARD_TYPES 1 /* support board types */
62
63 #define CONFIG_PREBOOT "echo;" \
64 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
65 "echo"
66
67 #undef CONFIG_BOOTARGS
68
69 #define CONFIG_EXTRA_ENV_SETTINGS \
70 "netdev=eth0\0" \
71 "nfsargs=setenv bootargs root=/dev/nfs rw " \
72 "nfsroot=${serverip}:${rootpath}\0" \
73 "ramargs=setenv bootargs root=/dev/ram rw\0" \
74 "addip=setenv bootargs ${bootargs} " \
75 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
76 ":${hostname}:${netdev}:off panic=1\0" \
77 "flash_nfs=run nfsargs addip;" \
78 "bootm ${kernel_addr}\0" \
79 "flash_self=run ramargs addip;" \
80 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
82 "rootpath=/opt/eldk/ppc_8xx\0" \
83 "hostname=TQM866M\0" \
84 "bootfile=TQM866M/uImage\0" \
85 "fdt_addr=400C0000\0" \
86 "kernel_addr=40100000\0" \
87 "ramdisk_addr=40280000\0" \
88 "u-boot=TQM866M/u-image.bin\0" \
89 "load=tftp 200000 ${u-boot}\0" \
90 "update=prot off 40000000 +${filesize};" \
91 "era 40000000 +${filesize};" \
92 "cp.b 200000 40000000 ${filesize};" \
93 "sete filesize;save\0" \
94 ""
95 #define CONFIG_BOOTCOMMAND "run flash_self"
96
97 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
98 #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
99
100 #undef CONFIG_WATCHDOG /* watchdog disabled */
101
102 #define CONFIG_STATUS_LED 1 /* Status LED enabled */
103
104 #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
105
106 /* enable I2C and select the hardware/software driver */
107 #undef CONFIG_HARD_I2C /* I2C with hardware support */
108 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
109
110 #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */
111 #define CONFIG_SYS_I2C_SLAVE 0xFE
112
113 #ifdef CONFIG_SOFT_I2C
114 /*
115 * Software (bit-bang) I2C driver configuration
116 */
117 #define PB_SCL 0x00000020 /* PB 26 */
118 #define PB_SDA 0x00000010 /* PB 27 */
119
120 #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
121 #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
122 #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
123 #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
124 #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
125 else immr->im_cpm.cp_pbdat &= ~PB_SDA
126 #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
127 else immr->im_cpm.cp_pbdat &= ~PB_SCL
128 #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
129 #endif /* CONFIG_SOFT_I2C */
130
131 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C256 */
132 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
133 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
134 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
135
136 /*
137 * BOOTP options
138 */
139 #define CONFIG_BOOTP_SUBNETMASK
140 #define CONFIG_BOOTP_GATEWAY
141 #define CONFIG_BOOTP_HOSTNAME
142 #define CONFIG_BOOTP_BOOTPATH
143 #define CONFIG_BOOTP_BOOTFILESIZE
144
145
146 #define CONFIG_MAC_PARTITION
147 #define CONFIG_DOS_PARTITION
148
149 #undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
150
151 #define CONFIG_TIMESTAMP /* but print image timestmps */
152
153
154 /*
155 * Command line configuration.
156 */
157 #include <config_cmd_default.h>
158
159 #define CONFIG_CMD_ASKENV
160 #define CONFIG_CMD_DHCP
161 #define CONFIG_CMD_EEPROM
162 #define CONFIG_CMD_ELF
163 #define CONFIG_CMD_IDE
164 #define CONFIG_CMD_JFFS2
165 #define CONFIG_CMD_NFS
166 #define CONFIG_CMD_SNTP
167
168
169 #define CONFIG_NETCONSOLE
170
171
172 /*
173 * Miscellaneous configurable options
174 */
175 #define CONFIG_SYS_LONGHELP /* undef to save memory */
176 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
177
178 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
179 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
180 #ifdef CONFIG_SYS_HUSH_PARSER
181 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
182 #endif
183
184 #if defined(CONFIG_CMD_KGDB)
185 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
186 #else
187 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
188 #endif
189 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
190 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
191 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
192
193 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
194 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
195
196 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
197
198 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
199
200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
201
202 /*
203 * Low Level Configuration Settings
204 * (address mappings, register initial values, etc.)
205 * You should know what you are doing if you make changes here.
206 */
207 /*-----------------------------------------------------------------------
208 * Internal Memory Mapped Register
209 */
210 #define CONFIG_SYS_IMMR 0xFFF00000
211
212 /*-----------------------------------------------------------------------
213 * Definitions for initial stack pointer and data area (in DPRAM)
214 */
215 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
216 #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
217 #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
218 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
219 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
220
221 /*-----------------------------------------------------------------------
222 * Start addresses for the final memory configuration
223 * (Set up by the startup code)
224 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
225 */
226 #define CONFIG_SYS_SDRAM_BASE 0x00000000
227 #define CONFIG_SYS_FLASH_BASE 0x40000000
228 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
229 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
230 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
231
232 /*
233 * For booting Linux, the board info and command line data
234 * have to be in the first 8 MB of memory, since this is
235 * the maximum mapped by the Linux kernel during initialization.
236 */
237 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
238
239 /*-----------------------------------------------------------------------
240 * FLASH organization
241 */
242 /* use CFI flash driver */
243 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
244 #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
245 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
246 #define CONFIG_SYS_FLASH_EMPTY_INFO
247 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
248 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
249 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
250
251 #define CONFIG_ENV_IS_IN_FLASH 1
252 #define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
253 #define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
254 #define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
255
256 /* Address and size of Redundant Environment Sector */
257 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
258 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
259
260 #define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
261
262 #define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
263
264 /*-----------------------------------------------------------------------
265 * Dynamic MTD partition support
266 */
267 #define CONFIG_JFFS2_CMDLINE
268 #define MTDIDS_DEFAULT "nor0=TQM8xxM-0"
269
270 #define MTDPARTS_DEFAULT "mtdparts=TQM8xxM-0:512k(u-boot)," \
271 "128k(dtb)," \
272 "1920k(kernel)," \
273 "5632(rootfs)," \
274 "4m(data)"
275
276 /*-----------------------------------------------------------------------
277 * Hardware Information Block
278 */
279 #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
280 #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
281 #define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
282
283 /*-----------------------------------------------------------------------
284 * Cache Configuration
285 */
286 #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
287 #if defined(CONFIG_CMD_KGDB)
288 #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
289 #endif
290
291 /*-----------------------------------------------------------------------
292 * SYPCR - System Protection Control 11-9
293 * SYPCR can only be written once after reset!
294 *-----------------------------------------------------------------------
295 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
296 */
297 #if defined(CONFIG_WATCHDOG)
298 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
299 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
300 #else
301 #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
302 #endif
303
304 /*-----------------------------------------------------------------------
305 * SIUMCR - SIU Module Configuration 11-6
306 *-----------------------------------------------------------------------
307 * PCMCIA config., multi-function pin tri-state
308 */
309 #ifndef CONFIG_CAN_DRIVER
310 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
311 #else /* we must activate GPL5 in the SIUMCR for CAN */
312 #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
313 #endif /* CONFIG_CAN_DRIVER */
314
315 /*-----------------------------------------------------------------------
316 * TBSCR - Time Base Status and Control 11-26
317 *-----------------------------------------------------------------------
318 * Clear Reference Interrupt Status, Timebase freezing enabled
319 */
320 #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
321
322 /*-----------------------------------------------------------------------
323 * PISCR - Periodic Interrupt Status and Control 11-31
324 *-----------------------------------------------------------------------
325 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
326 */
327 #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
328
329 /*-----------------------------------------------------------------------
330 * SCCR - System Clock and reset Control Register 15-27
331 *-----------------------------------------------------------------------
332 * Set clock output, timebase and RTC source and divider,
333 * power management and some other internal clocks
334 */
335 #define SCCR_MASK SCCR_EBDF11
336 #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
337 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
338 SCCR_DFALCD00)
339
340 /*-----------------------------------------------------------------------
341 * PCMCIA stuff
342 *-----------------------------------------------------------------------
343 *
344 */
345 #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
346 #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
347 #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
348 #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
349 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
350 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
351 #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
352 #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
353
354 /*-----------------------------------------------------------------------
355 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
356 *-----------------------------------------------------------------------
357 */
358
359 #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
360
361 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
362 #undef CONFIG_IDE_LED /* LED for ide not supported */
363 #undef CONFIG_IDE_RESET /* reset for ide not supported */
364
365 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
366 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
367
368 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
369
370 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
371
372 /* Offset for data I/O */
373 #define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
374
375 /* Offset for normal register accesses */
376 #define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
377
378 /* Offset for alternate registers */
379 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
380
381 /*-----------------------------------------------------------------------
382 *
383 *-----------------------------------------------------------------------
384 *
385 */
386 #define CONFIG_SYS_DER 0
387
388 /*
389 * Init Memory Controller:
390 *
391 * BR0/1 and OR0/1 (FLASH)
392 */
393
394 #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
395 #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
396
397 /* used to re-map FLASH both when starting from SRAM or FLASH:
398 * restrict access enough to keep SRAM working (if any)
399 * but not too much to meddle with FLASH accesses
400 */
401 #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
402 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
403
404 /*
405 * FLASH timing: Default value of OR0 after reset
406 */
407 #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
408 OR_SCY_15_CLK | OR_TRLX)
409
410 #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
411 #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
412 #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
413
414 #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
415 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
416 #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
417
418 /*
419 * BR2/3 and OR2/3 (SDRAM)
420 *
421 */
422 #define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
423 #define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
424 #define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
425
426 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
427 #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
428
429 #define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
430 #define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
431
432 #ifndef CONFIG_CAN_DRIVER
433 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
434 #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
435 #else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
436 #define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
437 #define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
438 #define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
439 #define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
440 BR_PS_8 | BR_MS_UPMB | BR_V )
441 #endif /* CONFIG_CAN_DRIVER */
442
443 /*
444 * 4096 Rows from SDRAM example configuration
445 * 1000 factor s -> ms
446 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
447 * 4 Number of refresh cycles per period
448 * 64 Refresh cycle in ms per number of rows
449 */
450 #define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
451
452 /*
453 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad)
454 *
455 * CPUclock(MHz) * 31.2
456 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0
457 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16
458 *
459 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us
460 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us
461 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us
462 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us
463 *
464 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will
465 * be met also in the default configuration, i.e. if environment variable
466 * 'cpuclk' is not set.
467 */
468 #define CONFIG_SYS_MAMR_PTA 97
469
470 /*
471 * Memory Periodic Timer Prescaler Register (MPTPR) values.
472 */
473 /* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */
474 #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
475 /* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */
476 #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
477
478 /*
479 * MAMR settings for SDRAM
480 */
481
482 /* 8 column SDRAM */
483 #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
484 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
485 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
486 /* 9 column SDRAM */
487 #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
488 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
489 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
490 /* 10 column SDRAM */
491 #define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
492 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
493 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
494
495 /*
496 * Internal Definitions
497 *
498 * Boot Flags
499 */
500 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
501 #define BOOTFLAG_WARM 0x02 /* Software reboot */
502
503 #define CONFIG_SCC1_ENET
504 #define CONFIG_FEC_ENET
505 #define CONFIG_ETHPRIME "SCC ETHERNET"
506
507 #endif /* __CONFIG_H */