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[people/ms/u-boot.git] / include / configs / XPEDITE5170.h
1 /*
2 * Copyright 2009 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * xpedite5170 board configuration file
26 */
27 #ifndef __CONFIG_H
28 #define __CONFIG_H
29
30 /*
31 * High Level Configuration Options
32 */
33 #define CONFIG_MPC86xx 1 /* MPC86xx */
34 #define CONFIG_MPC8641 1 /* MPC8641 specific */
35 #define CONFIG_XPEDITE5140 1 /* MPC8641HPCN board specific */
36 #define CONFIG_SYS_BOARD_NAME "XPedite5170"
37 #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */
38 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
39 #define CONFIG_BAT_RW 1 /* Use common BAT rw code */
40 #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */
41 #define CONFIG_ALTIVEC 1
42
43 #define CONFIG_SYS_TEXT_BASE 0xfff00000
44
45 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
46 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
47 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
48 #define CONFIG_PCIE1 1 /* PCIE controler 1 */
49 #define CONFIG_PCIE2 1 /* PCIE controler 2 */
50 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
51 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
52 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
53
54 /*
55 * DDR config
56 */
57 #define CONFIG_FSL_DDR2
58 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
59 #define CONFIG_DDR_SPD
60 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
61 #define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
62 #define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
63 #define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
64 #define CONFIG_NUM_DDR_CONTROLLERS 2
65 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
66 #define CONFIG_CHIP_SELECTS_PER_CTRL 1
67 #define CONFIG_DDR_ECC
68 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
69 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
70 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
71 #define CONFIG_VERY_BIG_RAM
72 #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */
73
74 /*
75 * virtual address to be used for temporary mappings. There
76 * should be 128k free at this VA.
77 */
78 #define CONFIG_SYS_SCRATCH_VA 0xe0000000
79
80 #ifndef __ASSEMBLY__
81 extern unsigned long get_board_sys_clk(unsigned long dummy);
82 #endif
83
84 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */
85
86 /*
87 * L2CR setup
88 */
89 #define CONFIG_SYS_L2
90 #define L2_INIT 0
91 #define L2_ENABLE (L2CR_L2E)
92
93 /*
94 * Base addresses -- Note these are effective addresses where the
95 * actual resources get mapped (not physical addresses)
96 */
97 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
98 #define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
99 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
100 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
101 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
102 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
103
104 /*
105 * Diagnostics
106 */
107 #define CONFIG_SYS_ALT_MEMTEST
108 #define CONFIG_SYS_MEMTEST_START 0x10000000
109 #define CONFIG_SYS_MEMTEST_END 0x20000000
110
111 /*
112 * Memory map
113 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
114 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
115 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
116 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
117 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
118 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
119 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
120 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
121 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
122 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
123 */
124
125 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3)
126
127 /*
128 * NAND flash configuration
129 */
130 #define CONFIG_SYS_NAND_BASE 0xef800000
131 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
132 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2}
133 #define CONFIG_SYS_MAX_NAND_DEVICE 2
134 #define CONFIG_NAND_ACTL
135 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */
136 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */
137 #define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */
138 #define CONFIG_SYS_NAND_ACTL_DELAY 25
139 #define CONFIG_SYS_NAND_QUIET_TEST
140 #define CONFIG_JFFS2_NAND
141
142 /*
143 * NOR flash configuration
144 */
145 #define CONFIG_SYS_FLASH_BASE 0xf8000000
146 #define CONFIG_SYS_FLASH_BASE2 0xf0000000
147 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
148 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
149 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
150 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
151 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
152 #define CONFIG_FLASH_CFI_DRIVER
153 #define CONFIG_SYS_FLASH_CFI
154 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
155 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \
156 {0xf7f00000, 0xc0000} }
157 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
158 #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */
159
160 /*
161 * Chip select configuration
162 */
163 /* NOR Flash 0 on CS0 */
164 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\
165 BR_PS_16 |\
166 BR_V)
167 #define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\
168 OR_GPCM_CSNT |\
169 OR_GPCM_XACS |\
170 OR_GPCM_ACS_DIV2 |\
171 OR_GPCM_SCY_8 |\
172 OR_GPCM_TRLX |\
173 OR_GPCM_EHTR |\
174 OR_GPCM_EAD)
175
176 /* NOR Flash 1 on CS1 */
177 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\
178 BR_PS_16 |\
179 BR_V)
180 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
181
182 /* NAND flash on CS2 */
183 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\
184 BR_PS_8 |\
185 BR_V)
186 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\
187 OR_GPCM_BCTLD |\
188 OR_GPCM_CSNT |\
189 OR_GPCM_ACS_DIV4 |\
190 OR_GPCM_SCY_4 |\
191 OR_GPCM_TRLX |\
192 OR_GPCM_EHTR)
193
194 /* Optional NAND flash on CS3 */
195 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\
196 BR_PS_8 |\
197 BR_V)
198 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
199
200 /*
201 * Use L1 as initial stack
202 */
203 #define CONFIG_SYS_INIT_RAM_LOCK 1
204 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
205 #define CONFIG_SYS_INIT_RAM_END 0x00004000
206
207 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
208 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
209 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
210
211 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
212 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
213
214 /*
215 * Serial Port
216 */
217 #define CONFIG_CONS_INDEX 1
218 #define CONFIG_SYS_NS16550
219 #define CONFIG_SYS_NS16550_SERIAL
220 #define CONFIG_SYS_NS16550_REG_SIZE 1
221 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
222 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
223 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
224 #define CONFIG_SYS_BAUDRATE_TABLE \
225 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
226 #define CONFIG_BAUDRATE 115200
227 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
228 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
229
230 /*
231 * Use the HUSH parser
232 */
233 #define CONFIG_SYS_HUSH_PARSER
234 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
235
236 /*
237 * Pass open firmware flat tree
238 */
239 #define CONFIG_OF_LIBFDT 1
240 #define CONFIG_OF_BOARD_SETUP 1
241 #define CONFIG_OF_STDOUT_VIA_ALIAS 1
242
243 /*
244 * I2C
245 */
246 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
247 #define CONFIG_HARD_I2C /* I2C with hardware support */
248 #define CONFIG_SYS_I2C_SPEED 100000 /* M41T00 only supports 100 KHz */
249 #define CONFIG_SYS_I2C_SLAVE 0x7F
250 #define CONFIG_SYS_I2C_OFFSET 0x3000
251 #define CONFIG_SYS_I2C2_OFFSET 0x3100
252 #define CONFIG_I2C_MULTI_BUS
253
254 /* PEX8518 slave I2C interface */
255 #define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
256
257 /* I2C DS1631 temperature sensor */
258 #define CONFIG_SYS_I2C_DS1621_ADDR 0x48
259 #define CONFIG_DTT_DS1621
260 #define CONFIG_DTT_SENSORS { 0 }
261
262 /* I2C EEPROM - AT24C128B */
263 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
264 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
265 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
266 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
267
268 /* I2C RTC */
269 #define CONFIG_RTC_M41T11 1
270 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
271 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
272
273 /* GPIO/EEPROM/SRAM */
274 #define CONFIG_DS4510
275 #define CONFIG_SYS_I2C_DS4510_ADDR 0x51
276
277 /* GPIO */
278 #define CONFIG_PCA953X
279 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
280 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
281 #define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
282 #define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
283 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
284
285 /*
286 * PU = pulled high, PD = pulled low
287 * I = input, O = output, IO = input/output
288 */
289 /* PCA9557 @ 0x18*/
290 #define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
291 #define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
292 #define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
293 #define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
294 #define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
295 #define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
296
297 /* PCA9557 @ 0x1c*/
298 #define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
299 #define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */
300 #define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
301 #define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
302 #define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
303 #define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
304 #define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
305 #define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
306
307 /* PCA9557 @ 0x1e*/
308 #define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
309 #define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
310 #define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
311 #define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
312 #define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
313 #define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */
314 #define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */
315
316 /* PCA9557 @ 0x1f */
317 #define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */
318 #define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */
319 #define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */
320 #define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */
321
322 /*
323 * General PCI
324 * Memory space is mapped 1-1, but I/O space must start from 0.
325 */
326 /* PCIE1 - PEX8518 */
327 #define CONFIG_SYS_PCIE1_MEM_BASE 0x80000000
328 #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
329 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
330 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
331 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
332 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
333
334 /* PCIE2 - VPX P1 */
335 #define CONFIG_SYS_PCIE2_MEM_BASE 0xc0000000
336 #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BASE
337 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
338 #define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
339 #define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
340 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
341
342 /*
343 * Networking options
344 */
345 #define CONFIG_TSEC_ENET /* tsec ethernet support */
346 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
347 #define CONFIG_NET_MULTI 1
348 #define CONFIG_MII 1 /* MII PHY management */
349 #define CONFIG_ETHPRIME "eTSEC1"
350
351 #define CONFIG_TSEC1 1
352 #define CONFIG_TSEC1_NAME "eTSEC1"
353 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
354 #define TSEC1_PHY_ADDR 1
355 #define TSEC1_PHYIDX 0
356 #define CONFIG_HAS_ETH0
357
358 #define CONFIG_TSEC2 1
359 #define CONFIG_TSEC2_NAME "eTSEC2"
360 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
361 #define TSEC2_PHY_ADDR 2
362 #define TSEC2_PHYIDX 0
363 #define CONFIG_HAS_ETH1
364
365 /*
366 * BAT mappings
367 */
368 #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
369 #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
370 BATL_PP_RW |\
371 BATL_CACHEINHIBIT |\
372 BATL_GUARDEDSTORAGE)
373 #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\
374 BATU_BL_1M |\
375 BATU_VS |\
376 BATU_VP)
377 #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\
378 BATL_PP_RW |\
379 BATL_CACHEINHIBIT)
380 #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
381 #endif
382
383 /*
384 * BAT0 2G Cacheable, non-guarded
385 * 0x0000_0000 2G DDR
386 */
387 #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
388 #define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
389 #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
390 #define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
391
392 /*
393 * BAT1 1G Cache-inhibited, guarded
394 * 0x8000_0000 1G PCI-Express 1 Memory
395 */
396 #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
397 BATL_PP_RW |\
398 BATL_CACHEINHIBIT |\
399 BATL_GUARDEDSTORAGE)
400 #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\
401 BATU_BL_1G |\
402 BATU_VS |\
403 BATU_VP)
404 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\
405 BATL_PP_RW |\
406 BATL_CACHEINHIBIT)
407 #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
408
409 /*
410 * BAT2 512M Cache-inhibited, guarded
411 * 0xc000_0000 512M PCI-Express 2 Memory
412 */
413 #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
414 BATL_PP_RW |\
415 BATL_CACHEINHIBIT |\
416 BATL_GUARDEDSTORAGE)
417 #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\
418 BATU_BL_512M |\
419 BATU_VS |\
420 BATU_VP)
421 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\
422 BATL_PP_RW |\
423 BATL_CACHEINHIBIT)
424 #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
425
426 /*
427 * BAT3 1M Cache-inhibited, guarded
428 * 0xe000_0000 1M CCSR
429 */
430 #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\
431 BATL_PP_RW |\
432 BATL_CACHEINHIBIT |\
433 BATL_GUARDEDSTORAGE)
434 #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\
435 BATU_BL_1M |\
436 BATU_VS |\
437 BATU_VP)
438 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\
439 BATL_PP_RW |\
440 BATL_CACHEINHIBIT)
441 #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
442
443 /*
444 * BAT4 32M Cache-inhibited, guarded
445 * 0xe200_0000 16M PCI-Express 1 I/O
446 * 0xe300_0000 16M PCI-Express 2 I/0
447 */
448 #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
449 BATL_PP_RW |\
450 BATL_CACHEINHIBIT |\
451 BATL_GUARDEDSTORAGE)
452 #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\
453 BATU_BL_32M |\
454 BATU_VS |\
455 BATU_VP)
456 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\
457 BATL_PP_RW |\
458 BATL_CACHEINHIBIT)
459 #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
460
461 /*
462 * BAT5 128K Cacheable, non-guarded
463 * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory)
464 */
465 #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\
466 BATL_PP_RW |\
467 BATL_MEMCOHERENCE)
468 #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\
469 BATU_BL_128K |\
470 BATU_VS |\
471 BATU_VP)
472 #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
473 #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
474
475 /*
476 * BAT6 256M Cache-inhibited, guarded
477 * 0xf000_0000 256M FLASH
478 */
479 #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\
480 BATL_PP_RW |\
481 BATL_CACHEINHIBIT |\
482 BATL_GUARDEDSTORAGE)
483 #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\
484 BATU_BL_256M |\
485 BATU_VS |\
486 BATU_VP)
487 #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\
488 BATL_PP_RW |\
489 BATL_MEMCOHERENCE)
490 #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
491
492 /* Map the last 1M of flash where we're running from reset */
493 #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
494 BATL_PP_RW |\
495 BATL_CACHEINHIBIT |\
496 BATL_GUARDEDSTORAGE)
497 #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\
498 BATU_BL_1M |\
499 BATU_VS |\
500 BATU_VP)
501 #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\
502 BATL_PP_RW |\
503 BATL_MEMCOHERENCE)
504 #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
505
506 /*
507 * BAT7 64M Cache-inhibited, guarded
508 * 0xe800_0000 64K NAND FLASH
509 * 0xe804_0000 128K DUART Registers
510 */
511 #define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\
512 BATL_PP_RW |\
513 BATL_CACHEINHIBIT |\
514 BATL_GUARDEDSTORAGE)
515 #define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\
516 BATU_BL_512K |\
517 BATU_VS |\
518 BATU_VP)
519 #define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\
520 BATL_PP_RW |\
521 BATL_CACHEINHIBIT)
522 #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
523
524 /*
525 * Command configuration.
526 */
527 #include <config_cmd_default.h>
528
529 #define CONFIG_CMD_ASKENV
530 #define CONFIG_CMD_DATE
531 #define CONFIG_CMD_DHCP
532 #define CONFIG_CMD_DS4510
533 #define CONFIG_CMD_DS4510_INFO
534 #define CONFIG_CMD_DTT
535 #define CONFIG_CMD_EEPROM
536 #define CONFIG_CMD_ELF
537 #define CONFIG_CMD_SAVEENV
538 #define CONFIG_CMD_FLASH
539 #define CONFIG_CMD_I2C
540 #define CONFIG_CMD_IRQ
541 #define CONFIG_CMD_JFFS2
542 #define CONFIG_CMD_MII
543 #define CONFIG_CMD_NAND
544 #define CONFIG_CMD_NET
545 #define CONFIG_CMD_PCA953X
546 #define CONFIG_CMD_PCA953X_INFO
547 #define CONFIG_CMD_PCI
548 #define CONFIG_CMD_PING
549 #define CONFIG_CMD_REGINFO
550 #define CONFIG_CMD_SNTP
551
552 /*
553 * Miscellaneous configurable options
554 */
555 #define CONFIG_SYS_LONGHELP /* undef to save memory */
556 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
557 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
558 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
559 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
560 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
561 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
562 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
563 #define CONFIG_CMDLINE_EDITING 1 /* Command-line editing */
564 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
565 #define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
566 #define CONFIG_PANIC_HANG /* do not reset board on panic */
567 #define CONFIG_PREBOOT /* enable preboot variable */
568 #define CONFIG_FIT 1
569 #define CONFIG_FIT_VERBOSE 1
570 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
571
572 /*
573 * For booting Linux, the board info and command line data
574 * have to be in the first 16 MB of memory, since this is
575 * the maximum mapped by the Linux kernel during initialization.
576 */
577 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
578 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
579
580 /*
581 * Environment Configuration
582 */
583 #define CONFIG_ENV_IS_IN_FLASH 1
584 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
585 #define CONFIG_ENV_SIZE 0x8000
586 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
587
588 /*
589 * Flash memory map:
590 * fffc0000 - ffffffff Pri FDT (256KB)
591 * fff80000 - fffbffff Pri U-Boot Environment (256 KB)
592 * fff00000 - fff7ffff Pri U-Boot (512 KB)
593 * fef00000 - ffefffff Pri OS image (16MB)
594 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
595 *
596 * f7fc0000 - f7ffffff Sec FDT (256KB)
597 * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB)
598 * f7f00000 - f7f7ffff Sec U-Boot (512 KB)
599 * f6f00000 - f7efffff Sec OS image (16MB)
600 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
601 */
602 #define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000)
603 #define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000)
604 #define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000)
605 #define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000)
606 #define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
607 #define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
608
609 #define CONFIG_PROG_UBOOT1 \
610 "$download_cmd $loadaddr $ubootfile; " \
611 "if test $? -eq 0; then " \
612 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
613 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
614 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
615 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
616 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
617 "if test $? -ne 0; then " \
618 "echo PROGRAM FAILED; " \
619 "else; " \
620 "echo PROGRAM SUCCEEDED; " \
621 "fi; " \
622 "else; " \
623 "echo DOWNLOAD FAILED; " \
624 "fi;"
625
626 #define CONFIG_PROG_UBOOT2 \
627 "$download_cmd $loadaddr $ubootfile; " \
628 "if test $? -eq 0; then " \
629 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
630 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
631 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
632 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
633 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
634 "if test $? -ne 0; then " \
635 "echo PROGRAM FAILED; " \
636 "else; " \
637 "echo PROGRAM SUCCEEDED; " \
638 "fi; " \
639 "else; " \
640 "echo DOWNLOAD FAILED; " \
641 "fi;"
642
643 #define CONFIG_BOOT_OS_NET \
644 "$download_cmd $osaddr $osfile; " \
645 "if test $? -eq 0; then " \
646 "if test -n $fdtaddr; then " \
647 "$download_cmd $fdtaddr $fdtfile; " \
648 "if test $? -eq 0; then " \
649 "bootm $osaddr - $fdtaddr; " \
650 "else; " \
651 "echo FDT DOWNLOAD FAILED; " \
652 "fi; " \
653 "else; " \
654 "bootm $osaddr; " \
655 "fi; " \
656 "else; " \
657 "echo OS DOWNLOAD FAILED; " \
658 "fi;"
659
660 #define CONFIG_PROG_OS1 \
661 "$download_cmd $osaddr $osfile; " \
662 "if test $? -eq 0; then " \
663 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
664 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
665 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
666 "if test $? -ne 0; then " \
667 "echo OS PROGRAM FAILED; " \
668 "else; " \
669 "echo OS PROGRAM SUCCEEDED; " \
670 "fi; " \
671 "else; " \
672 "echo OS DOWNLOAD FAILED; " \
673 "fi;"
674
675 #define CONFIG_PROG_OS2 \
676 "$download_cmd $osaddr $osfile; " \
677 "if test $? -eq 0; then " \
678 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
679 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
680 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
681 "if test $? -ne 0; then " \
682 "echo OS PROGRAM FAILED; " \
683 "else; " \
684 "echo OS PROGRAM SUCCEEDED; " \
685 "fi; " \
686 "else; " \
687 "echo OS DOWNLOAD FAILED; " \
688 "fi;"
689
690 #define CONFIG_PROG_FDT1 \
691 "$download_cmd $fdtaddr $fdtfile; " \
692 "if test $? -eq 0; then " \
693 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
694 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
695 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
696 "if test $? -ne 0; then " \
697 "echo FDT PROGRAM FAILED; " \
698 "else; " \
699 "echo FDT PROGRAM SUCCEEDED; " \
700 "fi; " \
701 "else; " \
702 "echo FDT DOWNLOAD FAILED; " \
703 "fi;"
704
705 #define CONFIG_PROG_FDT2 \
706 "$download_cmd $fdtaddr $fdtfile; " \
707 "if test $? -eq 0; then " \
708 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
709 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
710 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
711 "if test $? -ne 0; then " \
712 "echo FDT PROGRAM FAILED; " \
713 "else; " \
714 "echo FDT PROGRAM SUCCEEDED; " \
715 "fi; " \
716 "else; " \
717 "echo FDT DOWNLOAD FAILED; " \
718 "fi;"
719
720 #define CONFIG_EXTRA_ENV_SETTINGS \
721 "autoload=yes\0" \
722 "download_cmd=tftp\0" \
723 "console_args=console=ttyS0,115200\0" \
724 "root_args=root=/dev/nfs rw\0" \
725 "misc_args=ip=on\0" \
726 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
727 "bootfile=/home/user/file\0" \
728 "osfile=/home/user/uImage-XPedite5170\0" \
729 "fdtfile=/home/user/xpedite5170.dtb\0" \
730 "ubootfile=/home/user/u-boot.bin\0" \
731 "fdtaddr=c00000\0" \
732 "osaddr=0x1000000\0" \
733 "loadaddr=0x1000000\0" \
734 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
735 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
736 "prog_os1="CONFIG_PROG_OS1"\0" \
737 "prog_os2="CONFIG_PROG_OS2"\0" \
738 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
739 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
740 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
741 "bootcmd_flash1=run set_bootargs; " \
742 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
743 "bootcmd_flash2=run set_bootargs; " \
744 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
745 "bootcmd=run bootcmd_flash1\0"
746 #endif /* __CONFIG_H */
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