include/configs/a4m072.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2010
   6  * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  * (easy to change)
  33  */
  34
  35 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  36 #define CONFIG_MPC5200          1       /* (more precisely a MPC5200 CPU) */
  37 #define CONFIG_A4M072           1       /* ... on A4M072 board */
  38 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM */
  39
  40 #define CONFIG_SYS_TEXT_BASE    0xFE000000
  41
  42 #define CONFIG_MISC_INIT_R
  43
  44 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  45
  46 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  47
  48 /*
  49  * Serial console configuration
  50  */
  51 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  52 #define CONFIG_BAUDRATE         9600    /* ... at 9600 bps */
  53 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  54 /* define to enable silent console */
  55 #define CONFIG_SILENT_CONSOLE
  56 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
  57
  58 /*
  59  * PCI Mapping:
  60  * 0x40000000 - 0x4fffffff - PCI Memory
  61  * 0x50000000 - 0x50ffffff - PCI IO Space
  62  */
  63 #define CONFIG_PCI
  64
  65 #if defined(CONFIG_PCI)
  66 #define CONFIG_PCI_PNP          1
  67 #define CONFIG_PCI_SCAN_SHOW    1
  68 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  69
  70 #define CONFIG_PCI_MEM_BUS      0x40000000
  71 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  72 #define CONFIG_PCI_MEM_SIZE     0x10000000
  73
  74 #define CONFIG_PCI_IO_BUS       0x50000000
  75 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  76 #define CONFIG_PCI_IO_SIZE      0x01000000
  77 #endif
  78
  79 #define CONFIG_SYS_XLB_PIPELINING       1
  80
  81 #undef CONFIG_NET_MULTI
  82 #undef CONFIG_EEPRO100
  83
  84 /* Partitions */
  85 #define CONFIG_MAC_PARTITION
  86 #define CONFIG_DOS_PARTITION
  87
  88 /* USB */
  89 #define CONFIG_USB_OHCI_NEW
  90 #define CONFIG_USB_STORAGE
  91 #define CONFIG_SYS_OHCI_BE_CONTROLLER
  92 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
  93 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
  94 #define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
  95 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
  96 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
  97
  98 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  99
 100 /*
 101  * BOOTP options
 102  */
 103 #define CONFIG_BOOTP_BOOTFILESIZE
 104 #define CONFIG_BOOTP_BOOTPATH
 105 #define CONFIG_BOOTP_GATEWAY
 106 #define CONFIG_BOOTP_HOSTNAME
 107
 108
 109 /*
 110  * Command line configuration.
 111  */
 112 #include <config_cmd_default.h>
 113
 114 #define CONFIG_CMD_EEPROM
 115 #define CONFIG_CMD_FAT
 116 #define CONFIG_CMD_I2C
 117 #define CONFIG_CMD_IDE
 118 #define CONFIG_CMD_NFS
 119 #define CONFIG_CMD_SNTP
 120 #define CONFIG_CMD_USB
 121 #define CONFIG_CMD_MII
 122 #define CONFIG_CMD_DHCP
 123 #define CONFIG_CMD_PING
 124 #define CONFIG_CMD_DISPLAY
 125
 126 #if defined(CONFIG_PCI)
 127 #define CONFIG_CMD_PCI
 128 #endif
 129
 130 #if (CONFIG_SYS_TEXT_BASE == 0xFE000000)                /* Boot low with 32 MB Flash */
 131 #define CONFIG_SYS_LOWBOOT              1
 132 #define CONFIG_SYS_LOWBOOT32            1
 133 #endif
 134
 135 /*
 136  * Autobooting
 137  */
 138 #define CONFIG_BOOTDELAY        2       /* autoboot after 2 seconds */
 139
 140 #define CONFIG_SYS_AUTOLOAD     "n"
 141
 142 #define CONFIG_AUTOBOOT_KEYED
 143 #define CONFIG_AUTOBOOT_PROMPT          "autoboot in %d seconds\n", bootdelay
 144 #define CONFIG_AUTOBOOT_DELAY_STR       "asdfg"
 145
 146 #undef  CONFIG_BOOTARGS
 147 #define CONFIG_PREBOOT                          "run try_update"
 148
 149 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 150         "bk=run add_mtd ; run add_consolespec ; bootm 200000\0"         \
 151         "cf1=diskboot 200000 0:1\0"                                     \
 152         "bootcmd_cf1=run bcf1\0"                                        \
 153         "bcf=setenv bootargs root=/dev/hda3\0"                          \
 154         "bootcmd_nfs=run bnfs\0"                                        \
 155         "norargs=setenv bootargs root=/dev/mtdblock3 rootfstype=cramfs "\
 156                 "panic=1\0"                                             \
 157         "bootcmd_nor=cp.b ${kernel_addr} 200000 100000;"                \
 158                         "run norargs addip; run bk\0"                   \
 159         "bnfs=nfs 200000 ${rootpath}/boot/uImage;"                      \
 160                         "run nfsargs addip ; run bk\0"                  \
 161         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 162                                 "nfsroot=${serverip}:${rootpath}\0"     \
 163         "try_update=usb start;sleep 2;usb start;sleep 1;"               \
 164                         "fatload usb 0 2F0000 PCPUUPDT 2FF;usb stop;"   \
 165                         "source 2F0000\0"                               \
 166         "env_addr=FE060000\0"                                           \
 167         "kernel_addr=FE100000\0"                                        \
 168         "rootfs_addr=FE200000\0"                                        \
 169         "add_mtd=setenv bootargs ${bootargs} mtdparts="                 \
 170                 "phys_mapped_flash:384k(u),640k(e),1m(k),30m(r)\0"      \
 171         "bcf1=run cf1; run bcf; run addip; run bk\0"                    \
 172         "add_consolespec=setenv bootargs ${bootargs} "                  \
 173                                 "console=/dev/null quiet\0"             \
 174         "addip=if test -n ${ethaddr};"                                  \
 175                 "then if test -n ${ipaddr};"                            \
 176                         "then setenv bootargs ${bootargs} "             \
 177                                 "ip=${ipaddr}:${serverip}:${gatewayip}:"\
 178                                 "${netmask}:${hostname}:${netdev}:off;" \
 179                         "fi;"                                           \
 180                 "else;"                                                 \
 181                         "setenv bootargs ${bootargs} no_ethaddr;"       \
 182                 "fi\0"                                                  \
 183         "hostname=CPUP0\0"                                              \
 184         "ethaddr=00:00:00:00:00:00\0"                                   \
 185         "netdev=eth0\0"                                                 \
 186         "bootcmd=run bootcmd_nor\0"                                     \
 187         ""
 188 /*
 189  * IPB Bus clocking configuration.
 190  */
 191 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 192
 193 /*
 194  * I2C configuration
 195  */
 196 #define CONFIG_HARD_I2C                 1       /* I2C with hardware support */
 197 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 198
 199 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 200 #define CONFIG_SYS_I2C_SLAVE            0x7F
 201
 202 /*
 203  * EEPROM configuration
 204  */
 205 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x52    /* 1010010x */
 206 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 207 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 208 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 209 #define CONFIG_SYS_EEPROM_WREN                  1
 210 #define CONFIG_SYS_EEPROM_WP                    GPIO_PSC2_4
 211
 212 /*
 213  * Flash configuration
 214  */
 215 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 216 #define CONFIG_SYS_FLASH_SIZE           0x02000000
 217 #if !defined(CONFIG_SYS_LOWBOOT)
 218 #error "CONFIG_SYS_LOWBOOT not defined?"
 219 #else   /* CONFIG_SYS_LOWBOOT */
 220 #if defined(CONFIG_SYS_LOWBOOT32)
 221 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
 222 #endif
 223 #endif  /* CONFIG_SYS_LOWBOOT */
 224
 225 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks      */
 226 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 227 #define CONFIG_FLASH_CFI_DRIVER
 228 #define CONFIG_SYS_FLASH_CFI
 229 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 230 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_CS0_START}
 231 #define CONFIG_SYS_FLASH_BANKS_SIZES    {CONFIG_SYS_CS0_SIZE}
 232
 233 /*
 234  * Environment settings
 235  */
 236 #define CONFIG_ENV_IS_IN_FLASH  1
 237 #define CONFIG_ENV_SIZE         0x10000
 238 #define CONFIG_ENV_SECT_SIZE    0x20000
 239 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 240 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 241
 242 #define CONFIG_ENV_OVERWRITE    1
 243
 244 /*
 245  * Memory map
 246  */
 247 #define CONFIG_SYS_MBAR         0xF0000000
 248 #define CONFIG_SYS_SDRAM_BASE   0x00000000
 249 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 250
 251 /* Use SRAM until RAM will be available */
 252 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 253 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 254
 255
 256 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 257 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 258
 259 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 260 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 261 #   define CONFIG_SYS_RAMBOOT           1
 262 #endif
 263
 264 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 384 kB for Monitor   */
 265 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 266 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 267
 268 /*
 269  * Ethernet configuration
 270  */
 271 #define CONFIG_MPC5xxx_FEC      1
 272 #define CONFIG_MPC5xxx_FEC_MII100
 273 /*
 274  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 275  */
 276 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 277 #define CONFIG_PHY_ADDR         0x1f
 278 #define CONFIG_PHY_TYPE         0x79c874                /* AMD Phy Controller */
 279
 280 /*
 281  * GPIO configuration
 282  */
 283 #define CONFIG_SYS_GPS_PORT_CONFIG      0x18000004
 284
 285 /*
 286  * Miscellaneous configurable options
 287  */
 288 #define CONFIG_SYS_HUSH_PARSER
 289 #define CONFIG_CMDLINE_EDITING  1
 290 #ifdef CONFIG_SYS_HUSH_PARSER
 291 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 292 #endif
 293 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 294 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 295 #if defined(CONFIG_CMD_KGDB)
 296 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 297 #else
 298 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 299 #endif
 300 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 301 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 302 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 303
 304 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 305 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 306
 307 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 308
 309 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 310
 311 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 312 #if defined(CONFIG_CMD_KGDB)
 313 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 314 #endif
 315
 316
 317 /*
 318  * Various low-level settings
 319  */
 320 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 321 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 322 /* Flash at CSBoot, CS0 */
 323 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
 324 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 325 #define CONFIG_SYS_BOOTCS_CFG           0x0002DD00
 326 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 327 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 328 /* External SRAM at CS1 */
 329 #define CONFIG_SYS_CS1_START            0x62000000
 330 #define CONFIG_SYS_CS1_SIZE             0x00400000
 331 #define CONFIG_SYS_CS1_CFG              0x00009930
 332 #define CONFIG_SYS_SRAM_BASE            CONFIG_SYS_CS1_START
 333 #define CONFIG_SYS_SRAM_SIZE            CONFIG_SYS_CS1_SIZE
 334 /* LED display at CS7 */
 335 #define CONFIG_SYS_CS7_START            0x6a000000
 336 #define CONFIG_SYS_CS7_SIZE             (64*1024)
 337 #define CONFIG_SYS_CS7_CFG              0x0000bf30
 338
 339 #define CONFIG_SYS_CS_BURST             0x00000000
 340 #define CONFIG_SYS_CS_DEADCYCLE         0x33333003
 341
 342 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 343
 344 /*-----------------------------------------------------------------------
 345  * USB stuff
 346  *-----------------------------------------------------------------------
 347  */
 348 #define CONFIG_USB_CLOCK        0x0001BBBB
 349 #define CONFIG_USB_CONFIG       0x00001000 /* 0x4000 for SE mode */
 350
 351 /*-----------------------------------------------------------------------
 352  * IDE/ATA stuff Supports IDE harddisk
 353  *-----------------------------------------------------------------------
 354  */
 355
 356 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 357
 358 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 359 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 360
 361 #define CONFIG_IDE_PREINIT
 362
 363 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 364 #define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 2 drives per IDE bus    */
 365
 366 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 367
 368 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 369
 370 /* Offset for data I/O                  */
 371 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 372
 373 /* Offset for normal register accesses  */
 374 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 375
 376 /* Offset for alternate registers       */
 377 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 378
 379 /* Interval between registers                                                */
 380 #define CONFIG_SYS_ATA_STRIDE          4
 381
 382 #define CONFIG_ATAPI                   1
 383
 384 /*-----------------------------------------------------------------------
 385  * Open firmware flat tree support
 386  *-----------------------------------------------------------------------
 387  */
 388 #define CONFIG_OF_LIBFDT        1
 389 #define CONFIG_OF_BOARD_SETUP   1
 390
 391 #define OF_CPU                  "PowerPC,5200@0"
 392 #define OF_SOC                  "soc5200@f0000000"
 393 #define OF_TBCLK                (bd->bi_busfreq / 4)
 394 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
 395
 396 /* Support for the 7-segment display */
 397 #define CONFIG_SYS_DISP_CHR_RAM      CONFIG_SYS_CS7_START
 398 #define CONFIG_SHOW_ACTIVITY            /* used for display realization */
 399
 400 #define CONFIG_SHOW_BOOT_PROGRESS
 401
 402 #endif /* __CONFIG_H */