include/configs/aev.h

   1 /*
   2  * (C) Copyright 2003-2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2004-2005
   6  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  * (easy to change)
  33  */
  34
  35 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  36 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU) */
  37 #define CONFIG_TQM5200          1       /* ... on TQM5200 module */
  38 #undef CONFIG_TQM5200_REV100            /*  define for revision 100 modules */
  39 #define CONFIG_STK52XX          1       /* ... on a STK52XX base board */
  40 #define CONFIG_STK52XX_REV100   1       /*  define for revision 100 baseboards */
  41 #define CONFIG_AEVFIFO          1
  42 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz */
  43
  44 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  45 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  46
  47 /*
  48  * Serial console configuration
  49  */
  50 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  51 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  52 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  53
  54 /*
  55  * PCI Mapping:
  56  * 0x40000000 - 0x4fffffff - PCI Memory
  57  * 0x50000000 - 0x50ffffff - PCI IO Space
  58  */
  59 #ifdef CONFIG_AEVFIFO
  60 #define CONFIG_PCI              1
  61 #define CONFIG_PCI_PNP          1
  62 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  63 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE         1
  64
  65 #define CONFIG_PCI_MEM_BUS      0x40000000
  66 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  67 #define CONFIG_PCI_MEM_SIZE     0x10000000
  68
  69 #define CONFIG_PCI_IO_BUS       0x50000000
  70 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  71 #define CONFIG_PCI_IO_SIZE      0x01000000
  72
  73 #define CONFIG_NET_MULTI        1
  74 #define CONFIG_EEPRO100         1
  75 #define CFG_RX_ETH_BUFFER       8  /* use 8 rx buffer on eepro100  */
  76 #define CONFIG_NS8382X          1
  77 #endif  /* CONFIG_AEVFIFO */
  78
  79 /* Partitions */
  80 #define CONFIG_MAC_PARTITION
  81 #define CONFIG_DOS_PARTITION
  82 #define CONFIG_ISO_PARTITION
  83
  84 /* POST support */
  85 #define CONFIG_POST             (CFG_POST_MEMORY   | \
  86                                  CFG_POST_CPU      | \
  87                                  CFG_POST_I2C)
  88
  89 #ifdef CONFIG_POST
  90 /* preserve space for the post_word at end of on-chip SRAM */
  91 #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
  92 #endif
  93
  94
  95 /*
  96  * BOOTP options
  97  */
  98 #define CONFIG_BOOTP_BOOTFILESIZE
  99 #define CONFIG_BOOTP_BOOTPATH
 100 #define CONFIG_BOOTP_GATEWAY
 101 #define CONFIG_BOOTP_HOSTNAME
 102
 103
 104 /*
 105  * Command line configuration.
 106  */
 107 #include <config_cmd_default.h>
 108
 109 #define CONFIG_CMD_ASKENV
 110 #define CONFIG_CMD_DATE
 111 #define CONFIG_CMD_DHCP
 112 #define CONFIG_CMD_ECHO
 113 #define CONFIG_CMD_EEPROM
 114 #define CONFIG_CMD_I2C
 115 #define CONFIG_CMD_MII
 116 #define CONFIG_CMD_NFS
 117 #define CONFIG_CMD_PCI
 118 #define CONFIG_CMD_PING
 119 #define CONFIG_CMD_REGINFO
 120 #define CONFIG_CMD_SNTP
 121
 122 #ifdef CONFIG_POST
 123 #define CONFIG_CMD_DIAG
 124 #endif
 125
 126
 127 #define CONFIG_TIMESTAMP                /* display image timestamps */
 128
 129 #if (TEXT_BASE == 0xFC000000)           /* Boot low */
 130 #   define CFG_LOWBOOT          1
 131 #endif
 132
 133 /*
 134  * Autobooting
 135  */
 136 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 137
 138 #define CONFIG_PREBOOT  "echo;" \
 139         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 140         "echo"
 141
 142 #undef  CONFIG_BOOTARGS
 143
 144 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 145         "netdev=eth0\0"                                                 \
 146         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 147         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 148         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 149                 "nfsroot=${serverip}:${rootpath} "                      \
 150                 "console=ttyS0,${baudrate}\0"                           \
 151         "addip=setenv bootargs ${bootargs} "                            \
 152                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 153                 ":${hostname}:${netdev}:off panic=1\0"                  \
 154         "flash_self=run ramargs addip;"                                 \
 155                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 156         "flash_nfs=run nfsargs addip;"                                  \
 157                 "bootm ${kernel_addr}\0"                                \
 158         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 159         "bootfile=/tftpboot/tqm5200/uImage\0"                           \
 160         "load=tftp 200000 ${u-boot}\0"                                  \
 161         "u-boot=/tftpboot/tqm5200/u-boot.bin\0"                         \
 162         "update=protect off FC000000 FC05FFFF;"                         \
 163                 "erase FC000000 FC05FFFF;"                              \
 164                 "cp.b 200000 FC000000 ${filesize};"                     \
 165                 "protect on FC000000 FC05FFFF\0"                        \
 166         ""
 167
 168 #define CONFIG_BOOTCOMMAND      "run net_nfs"
 169
 170 /*
 171  * IPB Bus clocking configuration.
 172  */
 173 #define CFG_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
 174
 175 #if defined(CFG_IPBCLK_EQUALS_XLBCLK)
 176 /*
 177  * PCI Bus clocking configuration
 178  *
 179  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 180  * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 181  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 182  */
 183 #define CFG_PCICLK_EQUALS_IPBCLK_DIV2   /* define for 66MHz speed */
 184 #endif
 185
 186 /*
 187  * I2C configuration
 188  */
 189 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 190 #ifdef CONFIG_TQM5200_REV100
 191 #define CFG_I2C_MODULE          1       /* Select I2C module #1 for rev. 100 board */
 192 #else
 193 #define CFG_I2C_MODULE          2       /* Select I2C module #2 for all other revs */
 194 #endif
 195
 196 /*
 197  * I2C clock frequency
 198  *
 199  * Please notice, that the resulting clock frequency could differ from the
 200  * configured value. This is because the I2C clock is derived from system
 201  * clock over a frequency divider with only a few divider values. U-boot
 202  * calculates the best approximation for CFG_I2C_SPEED. However the calculated
 203  * approximation allways lies below the configured value, never above.
 204  */
 205 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 206 #define CFG_I2C_SLAVE           0x7F
 207
 208 /*
 209  * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
 210  * also). For other EEPROMs configuration should be verified. On Mini-FAP the
 211  * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
 212  * same configuration could be used.
 213  */
 214 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 215 #define CFG_I2C_EEPROM_ADDR_LEN         2
 216 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* =32 Bytes per write */
 217 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 218
 219 /*
 220  * Flash configuration
 221  */
 222 #define CFG_FLASH_BASE          TEXT_BASE /* 0xFC000000 */
 223
 224 /* use CFI flash driver if no module variant is spezified */
 225 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant */
 226 #define CFG_FLASH_CFI_DRIVER    1       /* Use the common driver */
 227 #define CFG_FLASH_BANKS_LIST    { CFG_BOOTCS_START }
 228 #define CFG_FLASH_EMPTY_INFO
 229 #define CFG_FLASH_SIZE          0x04000000 /* 64 MByte */
 230 #define CFG_MAX_FLASH_SECT      512     /* max num of sects on one chip */
 231 #undef CFG_FLASH_USE_BUFFER_WRITE       /* not supported yet for AMD */
 232
 233 #if !defined(CFG_LOWBOOT)
 234 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
 235 #else   /* CFG_LOWBOOT */
 236 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00060000)
 237 #endif  /* CFG_LOWBOOT */
 238 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks
 239                                            (= chip selects) */
 240 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 241 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 242
 243
 244 /*
 245  * Environment settings
 246  */
 247 #define CFG_ENV_IS_IN_FLASH     1
 248 #define CFG_ENV_SIZE            0x10000
 249 #define CFG_ENV_SECT_SIZE       0x20000
 250 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 251 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 252
 253 /*
 254  * Memory map
 255  */
 256 #define CFG_MBAR                0xF0000000
 257 #define CFG_SDRAM_BASE          0x00000000
 258 #define CFG_DEFAULT_MBAR        0x80000000
 259
 260 /* Use ON-Chip SRAM until RAM will be available */
 261 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 262 #ifdef CONFIG_POST
 263 /* preserve space for the post_word at end of on-chip SRAM */
 264 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_POST_SIZE
 265 #else
 266 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE
 267 #endif
 268
 269
 270 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 271 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 272 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 273
 274 #define CFG_MONITOR_BASE        TEXT_BASE
 275 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 276 #   define CFG_RAMBOOT          1
 277 #endif
 278
 279 #define CFG_MONITOR_LEN         (384 << 10)     /* Reserve 384 kB for Monitor   */
 280 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 281 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 282
 283 /*
 284  * Ethernet configuration
 285  */
 286 #define CONFIG_MPC5xxx_FEC      1
 287 /*
 288  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 289  */
 290 /* #define CONFIG_FEC_10MBIT 1 */
 291 #define CONFIG_PHY_ADDR         0x00
 292
 293 /*
 294  * GPIO configuration
 295  *
 296  * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
 297  *      Bit 0 (mask: 0x80000000): 1
 298  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 299  *      00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
 300  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
 301  *            Use for REV200 STK52XX boards. Do not use with REV100 modules
 302  *            (because, there I2C1 is used as I2C bus)
 303  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 304  * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
 305  *      000 -> All PSC2 pins are GIOPs
 306  *      001 -> CAN1/2 on PSC2 pins
 307  *             Use for REV100 STK52xx boards
 308  * use PSC6:
 309  *   on STK52xx:
 310  *      use as UART. Pins PSC6_0 to PSC6_3 are used.
 311  *      Bits 9:11 (mask: 0x00700000):
 312  *         101 -> PSC6 : Extended POST test is not available
 313  *   on MINI-FAP and TQM5200_IB:
 314  *      use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
 315  *         000 -> PSC6 could not be used as UART, CODEC or IrDA
 316  *   GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
 317  *   tests.
 318  */
 319 #define CFG_GPS_PORT_CONFIG     0x81500014
 320
 321 /*
 322  * RTC configuration
 323  */
 324 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 325
 326 /*
 327  * Miscellaneous configurable options
 328  */
 329 #define CFG_LONGHELP                    /* undef to save memory     */
 330 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 331 #if defined(CONFIG_CMD_KGDB)
 332 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 333 #else
 334 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 335 #endif
 336 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 337 #define CFG_MAXARGS             16      /* max number of command args   */
 338 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 339
 340 /* Enable an alternate, more extensive memory test */
 341 #define CFG_ALT_MEMTEST
 342
 343 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 344 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 345
 346 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 347
 348 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 349
 350 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
 351 #if defined(CONFIG_CMD_KGDB)
 352 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
 353 #endif
 354
 355 /*
 356  * Enable loopw command.
 357  */
 358 #define CONFIG_LOOPW
 359
 360 /*
 361  * Various low-level settings
 362  */
 363 #if defined(CONFIG_MPC5200)
 364 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 365 #define CFG_HID0_FINAL          HID0_ICE
 366 #else
 367 #define CFG_HID0_INIT           0
 368 #define CFG_HID0_FINAL          0
 369 #endif
 370
 371 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 372 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 373 #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2
 374 #define CFG_BOOTCS_CFG          0x0008DF30 /* for pci_clk  = 66 MHz */
 375 #else
 376 #define CFG_BOOTCS_CFG          0x0004DF30 /* for pci_clk = 33 MHz */
 377 #endif
 378 #define CFG_CS0_START           CFG_FLASH_BASE
 379 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 380
 381 #define CONFIG_LAST_STAGE_INIT
 382
 383 /*
 384  * SRAM - Do not map below 2 GB in address space, because this area is used
 385  * for SDRAM autosizing.
 386  */
 387 #define CFG_CS2_START           0xE5000000
 388 #define CFG_CS2_SIZE            0x80000         /* 512 kByte */
 389 #define CFG_CS2_CFG             0x0004D930
 390
 391 /*
 392  * Grafic controller - Do not map below 2 GB in address space, because this
 393  * area is used for SDRAM autosizing.
 394  */
 395 #define SM501_FB_BASE           0xE0000000
 396 #define CFG_CS1_START           (SM501_FB_BASE)
 397 #define CFG_CS1_SIZE            0x4000000       /* 64 MByte */
 398 #define CFG_CS1_CFG             0x8F48FF70
 399 #define SM501_MMIO_BASE         CFG_CS1_START + 0x03E00000
 400
 401 #define CFG_CS_BURST            0x00000000
 402 #define CFG_CS_DEADCYCLE        0x33333311      /* 1 dead cycle for flash and SM501 */
 403
 404 #define CFG_RESET_ADDRESS       0xff000000
 405
 406 #endif /* __CONFIG_H */