include/configs/alpr.h

   1 /*
   2  * (C) Copyright 2006
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*-----------------------------------------------------------------------
  28  * High Level Configuration Options
  29  *----------------------------------------------------------------------*/
  30 #define CONFIG_ALPR             1           /* Board is ebony           */
  31 #define CONFIG_440GX            1           /* Specifc GX support       */
  32 #define CONFIG_4xx              1           /* ... PPC4xx family        */
  33 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_pre_init      */
  34 #define CONFIG_LAST_STAGE_INIT  1           /* call last_stage_init()   */
  35 #undef  CFG_DRAM_TEST                       /* Disable-takes long time! */
  36 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  37
  38 /*-----------------------------------------------------------------------
  39  * Base addresses -- Note these are effective addresses where the
  40  * actual resources get mapped (not physical addresses)
  41  *----------------------------------------------------------------------*/
  42 #define CFG_SDRAM_BASE          0x00000000      /* _must_ be 0                  */
  43 #define CFG_FLASH_BASE          0xffe00000      /* start of FLASH               */
  44 #define CFG_MONITOR_BASE        0xfffc0000      /* start of monitor             */
  45 #define CFG_PCI_MEMBASE         0x80000000      /* mapped pci memory            */
  46 #define CFG_PCI_MEMSIZE         0x40000000      /* size of mapped pci memory    */
  47 #define CFG_PERIPHERAL_BASE     0xe0000000      /* internal peripherals         */
  48 #define CFG_ISRAM_BASE          0xc0000000      /* internal SRAM                */
  49 #define CFG_PCI_BASE            0xd0000000      /* internal PCI regs            */
  50 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
  51 #define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
  52 #define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
  53
  54
  55 #define CFG_FPGA_BASE       (CFG_PERIPHERAL_BASE + 0x08300000)
  56 #define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
  57
  58 /*-----------------------------------------------------------------------
  59  * Initial RAM & stack pointer (placed in internal SRAM)
  60  *----------------------------------------------------------------------*/
  61 #define CFG_TEMP_STACK_OCM  1
  62 #define CFG_OCM_DATA_ADDR   CFG_ISRAM_BASE
  63 #define CFG_INIT_RAM_ADDR   CFG_ISRAM_BASE  /* Initial RAM address      */
  64 #define CFG_INIT_RAM_END    0x2000          /* End of used area in RAM  */
  65 #define CFG_GBL_DATA_SIZE   128             /* num bytes initial data   */
  66
  67 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  68 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
  69 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
  70
  71 #define CFG_MONITOR_LEN     (256 * 1024)    /* Reserve 256 kB for Mon   */
  72 #define CFG_MALLOC_LEN      (128 * 1024)    /* Reserve 128 kB for malloc*/
  73
  74 /*-----------------------------------------------------------------------
  75  * Serial Port
  76  *----------------------------------------------------------------------*/
  77 #undef  CFG_EXT_SERIAL_CLOCK
  78 #define CONFIG_BAUDRATE         115200
  79 #define CONFIG_UART1_CONSOLE            /* define for uart1 as console  */
  80
  81 #define CFG_BAUDRATE_TABLE  \
  82     {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  83
  84 /*-----------------------------------------------------------------------
  85  * FLASH related
  86  *----------------------------------------------------------------------*/
  87 #define CFG_FLASH_CFI           1       /* The flash is CFI compatible          */
  88 #define CFG_FLASH_CFI_DRIVER    1       /* Use common CFI driver                */
  89 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
  90 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
  91 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
  92 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
  93 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash        */
  94
  95 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
  96
  97 #define CFG_ENV_SECT_SIZE       0x10000         /* size of one complete sector  */
  98 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
  99 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 100
 101 /* Address and size of Redundant Environment Sector     */
 102 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 103 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 104
 105 /*-----------------------------------------------------------------------
 106  * DDR SDRAM
 107  *----------------------------------------------------------------------*/
 108 #undef CONFIG_SPD_EEPROM                /* Don't use SPD EEPROM for setup       */
 109 #define CONFIG_SDRAM_BANK0      1       /* init onboard DDR SDRAM bank 0        */
 110 #undef CONFIG_SDRAM_ECC                 /* enable ECC support                   */
 111 #define CFG_SDRAM_TABLE { \
 112                 {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
 113                 {(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)  */
 114
 115 /*-----------------------------------------------------------------------
 116  * I2C
 117  *----------------------------------------------------------------------*/
 118 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 119 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 120 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address  */
 121 #define CFG_I2C_SLAVE           0x7F
 122 #define CFG_I2C_NOPROBES        {0x69}  /* Don't probe these addrs      */
 123
 124 /*-----------------------------------------------------------------------
 125  * I2C EEPROM (PCF8594C)
 126  *----------------------------------------------------------------------*/
 127 #define CFG_I2C_EEPROM_ADDR     0x54    /* EEPROM PCF8594C              */
 128 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 129 /* mask of address bits that overflow into the "EEPROM chip address"    */
 130 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x07
 131 #define CFG_EEPROM_PAGE_WRITE_BITS 3    /* The Philips PCF8594C has     */
 132                                         /* 8 byte page write mode using */
 133                                         /* last 3 bits of the address   */
 134 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  40   /* and takes up to 40 msec */
 135 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 136
 137 #define CONFIG_PREBOOT  "echo;" \
 138         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 139         "echo"
 140
 141 #undef  CONFIG_BOOTARGS
 142
 143 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 144         "netdev=eth3\0"                                                 \
 145         "hostname=alpr\0"                                               \
 146         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 147                 "nfsroot=${serverip}:${rootpath}\0"                     \
 148         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 149         "addip=setenv bootargs ${bootargs} "                            \
 150                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 151                 ":${hostname}:${netdev}:off panic=1\0"                  \
 152         "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
 153                 "mem=193M\0"                                            \
 154         "flash_nfs=run nfsargs addip addtty;"                           \
 155                 "bootm ${kernel_addr}\0"                                \
 156         "flash_self=run ramargs addip addtty;"                          \
 157                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 158         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 159                 "bootm\0"                                               \
 160         "rootpath=/opt/projects/alpr/nfs_root\0"                        \
 161         "bootfile=/alpr/uImage\0"                                       \
 162         "kernel_addr=fff00000\0"                                        \
 163         "ramdisk_addr=fff10000\0"                                       \
 164         "load=tftp 100000 /alpr/u-boot/u-boot.bin\0"                    \
 165         "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"   \
 166                 "cp.b 100000 fffc0000 40000;"                           \
 167                 "setenv filesize;saveenv\0"                             \
 168         "upd=run load;run update\0"                                     \
 169         "ethprime=ppc_4xx_eth3\0"                                       \
 170         "ethact=ppc_4xx_eth3\0"                                         \
 171         "autoload=no\0"                                                 \
 172         "ipconfig=dhcp;setenv serverip 11.0.0.152\0"                    \
 173         "actkernel=kernel2\0"                                           \
 174         "load_fpga=fpga load 0 ffe00000 10dd9a\0"                       \
 175         "mtdargs=setenv bootargs root=/dev/mtdblock6 rw "               \
 176                 "rootfstype=jffs2 init=/sbin/init\0"                    \
 177         "kernel1_mtd=nand read 200000 0 200000;run mtdargs addip addtty"\
 178                 ";bootm 200000\0"                                       \
 179         "kernel2_mtd=nand read 200000 200000 200000;run mtdargs addip " \
 180                 "addtty;bootm 200000\0"                                 \
 181         "kernel1=run ipconfig load_fpga kernel1_mtd\0"                  \
 182         "kernel2=run ipconfig load_fpga kernel2_mtd\0"                  \
 183         ""
 184
 185 #define CONFIG_BOOTCOMMAND      "run kernel2"
 186
 187 #define CONFIG_BOOTDELAY        2       /* autoboot after 5 seconds     */
 188
 189 #define CONFIG_BAUDRATE         115200
 190
 191 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 192 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 193
 194 #define CONFIG_MII              1       /* MII PHY management           */
 195 #define CONFIG_NET_MULTI        1
 196 #define CONFIG_PHY_ADDR         0x02    /* dummy setting, no EMAC0 used */
 197 #define CONFIG_PHY1_ADDR        0x03    /* dummy setting, no EMAC1 used */
 198 #define CONFIG_PHY2_ADDR        0x01    /* PHY address for EMAC2        */
 199 #define CONFIG_PHY3_ADDR        0x02    /* PHY address for EMAC3        */
 200 #define CONFIG_HAS_ETH0
 201 #define CONFIG_HAS_ETH1
 202 #define CONFIG_HAS_ETH2
 203 #define CONFIG_HAS_ETH3
 204 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 205 #define CONFIG_M88E1111_PHY     1       /* needed for PHY specific setup*/
 206 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 207 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 208
 209 #define CONFIG_NETCONSOLE               /* include NetConsole support   */
 210
 211 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
 212                                 CFG_CMD_ASKENV  | \
 213                                 CFG_CMD_DHCP    | \
 214                                 CFG_CMD_DIAG    | \
 215                                 CFG_CMD_EEPROM  | \
 216                                 CFG_CMD_ELF     | \
 217                                 CFG_CMD_I2C     | \
 218                                 CFG_CMD_IRQ     | \
 219                                 CFG_CMD_MII     | \
 220                                 CFG_CMD_NET     | \
 221                                 CFG_CMD_NFS     | \
 222                                 CFG_CMD_PCI     | \
 223                                 CFG_CMD_PING    | \
 224                                 CFG_CMD_FPGA    | \
 225                                 CFG_CMD_NAND    | \
 226                                 CFG_CMD_REGINFO)
 227
 228 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 229 #include <cmd_confdefs.h>
 230
 231 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 232
 233 /*
 234  * Miscellaneous configurable options
 235  */
 236 #define CFG_LONGHELP                    /* undef to save memory         */
 237 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 238 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 239 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 240 #else
 241 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 242 #endif
 243 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 244 #define CFG_MAXARGS     16              /* max number of command args   */
 245 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 246
 247 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 248 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 249
 250 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 251 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 252
 253 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 254
 255 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 256 #define CONFIG_LOOPW            1       /* enable loopw command         */
 257 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 258 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 259 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 260
 261 #define CFG_4xx_RESET_TYPE      0x2     /* use chip reset on this board */
 262
 263 /*-----------------------------------------------------------------------
 264  * PCI stuff
 265  *-----------------------------------------------------------------------
 266  */
 267 /* General PCI */
 268 #define CONFIG_PCI                      /* include pci support          */
 269 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 270 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 271 #define CFG_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CFG_PCI_MEMBASE */
 272 #define CONFIG_PCI_BOOTDELAY    1       /* enable pci bootdelay variable*/
 273
 274 /* Board-specific PCI */
 275 #define CFG_PCI_PRE_INIT                /* enable board pci_pre_init()  */
 276 #define CFG_PCI_TARGET_INIT             /* let board init pci target    */
 277 #define CFG_PCI_MASTER_INIT
 278
 279 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC */
 280 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
 281
 282 /*-----------------------------------------------------------------------
 283  * FPGA stuff
 284  *-----------------------------------------------------------------------*/
 285 #define CONFIG_FPGA             CFG_ALTERA_CYCLON2
 286 #define CFG_FPGA_CHECK_CTRLC
 287 #define CFG_FPGA_PROG_FEEDBACK
 288 #define CONFIG_FPGA_COUNT       1               /* Ich habe 2 ... aber in
 289                                         Reihe geschaltet -> sollte gehen,
 290                                         aufpassen mit Datasize ist jetzt
 291                                         halt doppelt so gross ... Seite 306
 292                                         ist das mit den multiple Device in PS
 293                                         Mode erklaert ...*/
 294
 295 /* FPGA program pin configuration */
 296 #define CFG_GPIO_CLK            18      /* FPGA clk pin (cpu output)            */
 297 #define CFG_GPIO_DATA           19      /* FPGA data pin (cpu output)           */
 298 #define CFG_GPIO_STATUS         20      /* FPGA status pin (cpu input)          */
 299 #define CFG_GPIO_CONFIG         21      /* FPGA CONFIG pin (cpu output)         */
 300 #define CFG_GPIO_CON_DON        22      /* FPGA CONFIG_DONE pin (cpu input)     */
 301
 302 #define CFG_GPIO_SEL_DPR        14      /* cpu output */
 303 #define CFG_GPIO_SEL_AVR        15      /* cpu output */
 304 #define CFG_GPIO_PROG_EN        23      /* cpu output */
 305
 306 /*-----------------------------------------------------------------------
 307  * Definitions for GPIO setup
 308  *-----------------------------------------------------------------------*/
 309 #define CFG_GPIO_SHUTDOWN       (0x80000000 >> 6)
 310 #define CFG_GPIO_SSD_EMPTY      (0x80000000 >> 9)
 311 #define CFG_GPIO_EREADY         (0x80000000 >> 26)
 312 #define CFG_GPIO_REV0           (0x80000000 >> 14)
 313 #define CFG_GPIO_REV1           (0x80000000 >> 15)
 314
 315 /*-----------------------------------------------------------------------
 316  * NAND-FLASH stuff
 317  *-----------------------------------------------------------------------*/
 318 #define CFG_MAX_NAND_DEVICE     4
 319 #define NAND_MAX_CHIPS          CFG_MAX_NAND_DEVICE
 320 #define CFG_NAND_BASE           0xF0000000      /* NAND FLASH Base Address      */
 321 #define CFG_NAND_BASE_LIST      { CFG_NAND_BASE + 0, CFG_NAND_BASE + 2, \
 322                                   CFG_NAND_BASE + 4, CFG_NAND_BASE + 6 }
 323 #define CFG_NAND_QUIET_TEST     1       /* don't warn upon unknown NAND flash   */
 324
 325 /*-----------------------------------------------------------------------
 326  * External Bus Controller (EBC) Setup
 327  *----------------------------------------------------------------------*/
 328 #define CFG_FLASH               CFG_FLASH_BASE
 329
 330 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 331 #define CFG_EBC_PB0AP           0x92015480
 332 #define CFG_EBC_PB0CR           (CFG_FLASH | 0x3A000) /* BS=2MB,BU=R/W,BW=16bit */
 333
 334 /* Memory Bank 1 (NAND-FLASH) initialization                                    */
 335 #define CFG_EBC_PB1AP           0x01840380      /* TWT=3                        */
 336 #define CFG_EBC_PB1CR           (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
 337
 338 /*
 339  * For booting Linux, the board info and command line data
 340  * have to be in the first 8 MB of memory, since this is
 341  * the maximum mapped by the Linux kernel during initialization.
 342  */
 343 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 344 /*-----------------------------------------------------------------------
 345  * Cache Configuration
 346  */
 347 #define CFG_DCACHE_SIZE         32768   /* For AMCC 440 CPUs                    */
 348 #define CFG_CACHELINE_SIZE      32      /* ...                  */
 349 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value        */
 350
 351 /*
 352  * Internal Definitions
 353  *
 354  * Boot Flags
 355  */
 356 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 357 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 358
 359 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 360 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 361 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 362 #endif
 363 #endif  /* __CONFIG_H */