include/configs/assabet.h

   1 /*
   2  * (C) Copyright 2002
   3  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4  * Marius Groeger <mgroeger@sysgo.de>
   5  *
   6  * 2004 (c) MontaVista Software, Inc.
   7  *
   8  * Configuation settings for the Intel Assabet board.
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #ifndef __CONFIG_H
  30 #define __CONFIG_H
  31
  32 #undef DEBUG
  33
  34 /*
  35  * High Level Configuration Options
  36  * (easy to change)
  37  */
  38 #define CONFIG_SA1110           1       /* This is an SA1100 CPU        */
  39 #define CONFIG_ASSABET          1       /* on an Intel Assabet Board    */
  40
  41 #undef CONFIG_USE_IRQ
  42
  43 #define CONFIG_CMDLINE_TAG       1      /* enable passing of ATAGs      */
  44 #define CONFIG_SETUP_MEMORY_TAGS 1
  45 #define CONFIG_INITRD_TAG        1
  46
  47 /*
  48  * Size of malloc() pool
  49  */
  50 #define CFG_MALLOC_LEN          (CFG_ENV_SIZE + 128*1024)
  51 #define CFG_GBL_DATA_SIZE       128     /* size rsrvd for initial data */
  52
  53 /*
  54  * Hardware drivers
  55  */
  56 #define CONFIG_DRIVER_LAN91C96  /* we have an SMC9194 on-board */
  57 #define CONFIG_LAN91C96_BASE    0x18000000
  58
  59 /*
  60  * select serial console configuration
  61  */
  62 #define CONFIG_SERIAL1          1       /* we use SERIAL 1 on Intel Assabet */
  63
  64 /* allow to overwrite serial and ethaddr */
  65 #define CONFIG_ENV_OVERWRITE
  66
  67 #define CONFIG_BAUDRATE         115200
  68
  69
  70 /*
  71  * Command line configuration.
  72  */
  73 #include <config_cmd_default.h>
  74
  75 #define CONFIG_CMD_DHCP
  76
  77
  78 /*
  79  * BOOTP options
  80  */
  81 #define CONFIG_BOOTP_SUBNETMASK
  82 #define CONFIG_BOOTP_GATEWAY
  83 #define CONFIG_BOOTP_HOSTNAME
  84 #define CONFIG_BOOTP_BOOTPATH
  85
  86
  87 #define CONFIG_BOOTDELAY        3
  88 #define CONFIG_BOOTARGS         "console=ttySA0,115200n8 root=/dev/nfs ip=bootp"
  89 #define CONFIG_BOOTCOMMAND      "bootp;tftp;bootm"
  90 #define CFG_AUTOLOAD            "n"     /* No autoload */
  91
  92 #if defined(CONFIG_CMD_KGDB)
  93 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port */
  94 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
  95 #endif
  96
  97 /*
  98  * Miscellaneous configurable options
  99  */
 100 #define CFG_LONGHELP            /* undef to save memory         */
 101 #define CFG_PROMPT              "Intel Assabet # "      /* Monitor Command Prompt       */
 102 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 103 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 104 #define CFG_MAXARGS             16      /* max number of command args   */
 105 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 106
 107 #define CFG_MEMTEST_START       0xc0400000      /* memtest works on     */
 108 #define CFG_MEMTEST_END         0xc0800000      /* 4 ... 8 MB in DRAM   */
 109
 110 #undef  CFG_CLKS_IN_HZ
 111
 112 #define CFG_LOAD_ADDR           0xc0000000      /* default load address */
 113
 114 #define CFG_HZ                  3686400 /* incrementer freq: 3.6864 MHz */
 115 #define CFG_CPUSPEED            0x0a    /* set core clock to 206MHz */
 116
 117                                                 /* valid baudrates */
 118 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 119
 120 /*-----------------------------------------------------------------------
 121  * Stack sizes
 122  *
 123  * The stack sizes are set up in start.S using the settings below
 124  */
 125 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 126 #ifdef CONFIG_USE_IRQ
 127 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 128 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 129 #endif
 130
 131 /*-----------------------------------------------------------------------
 132  * Physical Memory Map
 133  */
 134 #define CONFIG_NR_DRAM_BANKS    1       /* we have 1 bank of SDRAM */
 135 #define PHYS_SDRAM_1            0xc0000000      /* SDRAM Bank #1 */
 136 #define PHYS_SDRAM_1_SIZE       0x02000000      /* 32 MB */
 137
 138 #define PHYS_FLASH_1            0x00000000      /* Flash Bank #1 */
 139 #define PHYS_FLASH_SIZE         0x02000000      /* 32 MB */
 140 #define PHYS_FLASH_BANK_SIZE    0x01000000      /* 16 MB Banks */
 141 #define PHYS_FLASH_SECT_SIZE    0x00040000      /* 256 KB sectors (x2) */
 142
 143 #define CFG_MONITOR_BASE        TEXT_BASE
 144 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 KB for Monitor */
 145
 146 #if CFG_MONITOR_BASE < CFG_FLASH_BASE
 147 #define CFG_RAMSTART
 148 #endif
 149
 150 /*-----------------------------------------------------------------------
 151  * FLASH and environment organization
 152  */
 153
 154 #define CFG_FLASH_BASE          PHYS_FLASH_1
 155 #define CFG_FLASH_SIZE          PHYS_FLASH_SIZE
 156 #define CFG_FLASH_CFI           1       /* flash is CFI conformant      */
 157 #define CFG_FLASH_CFI_DRIVER    1       /* use common cfi driver        */
 158 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster) */
 159 #define CFG_MAX_FLASH_BANKS     1       /* max # of memory banks        */
 160 #define CFG_FLASH_INCREMENT     0       /* there is only one bank       */
 161 #define CFG_MAX_FLASH_SECT      128     /* max # of sectors on one chip */
 162 #undef CFG_FLASH_PROTECTION
 163 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 164
 165 #define CFG_ENV_IS_IN_FLASH     1
 166
 167 #if defined(CFG_ENV_IS_IN_FLASH)
 168 #define CFG_ENV_IN_OWN_SECTOR   1
 169 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
 170 #define CFG_ENV_SIZE            PHYS_FLASH_SECT_SIZE
 171 #define CFG_ENV_SECT_SIZE       PHYS_FLASH_SECT_SIZE
 172 #endif
 173
 174 #endif /* __CONFIG_H */