include/configs/at91rm9200dk.h

   1 /*
   2  * Rick Bronson <rick@efn.org>
   3  *
   4  * Configuation settings for the AT91RM9200DK board.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 /* ARM asynchronous clock */
  29 #define AT91C_MAIN_CLOCK        179712000       /* from 18.432 MHz crystal (18432000 / 4 * 39) */
  30 #define AT91C_MASTER_CLOCK      59904000        /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
  31 /* #define AT91C_MASTER_CLOCK   44928000 */     /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
  32
  33 #define AT91_SLOW_CLOCK         32768   /* slow clock */
  34
  35 #define CONFIG_ARM920T          1       /* This is an ARM920T Core      */
  36 #define CONFIG_AT91RM9200       1       /* It's an Atmel AT91RM9200 SoC */
  37 #define CONFIG_AT91RM9200DK     1       /* on an AT91RM9200DK Board     */
  38 #undef  CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff  */
  39 #define USE_920T_MMU            1
  40
  41 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs      */
  42 #define CONFIG_SETUP_MEMORY_TAGS 1
  43 #define CONFIG_INITRD_TAG       1
  44
  45 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  46 #define CONFIG_SYS_USE_MAIN_OSCILLATOR          1
  47 /* flash */
  48 #define MC_PUIA_VAL     0x00000000
  49 #define MC_PUP_VAL      0x00000000
  50 #define MC_PUER_VAL     0x00000000
  51 #define MC_ASR_VAL      0x00000000
  52 #define MC_AASR_VAL     0x00000000
  53 #define EBI_CFGR_VAL    0x00000000
  54 #define SMC_CSR0_VAL    0x00003284 /* 16bit, 2 TDF, 4 WS */
  55
  56 /* clocks */
  57 #define PLLAR_VAL       0x20263E04 /* 179.712000 MHz for PCK */
  58 #define PLLBR_VAL       0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  59 #define MCKR_VAL        0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
  60
  61 /* sdram */
  62 #define PIOC_ASR_VAL    0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  63 #define PIOC_BSR_VAL    0x00000000
  64 #define PIOC_PDR_VAL    0xFFFF0000
  65 #define EBI_CSA_VAL     0x00000002 /* CS1=SDRAM */
  66 #define SDRC_CR_VAL     0x2188c155 /* set up the SDRAM */
  67 #define SDRAM           0x20000000 /* address of the SDRAM */
  68 #define SDRAM1          0x20000080 /* address of the SDRAM */
  69 #define SDRAM_VAL       0x00000000 /* value written to SDRAM */
  70 #define SDRC_MR_VAL     0x00000002 /* Precharge All */
  71 #define SDRC_MR_VAL1    0x00000004 /* refresh */
  72 #define SDRC_MR_VAL2    0x00000003 /* Load Mode Register */
  73 #define SDRC_MR_VAL3    0x00000000 /* Normal Mode */
  74 #define SDRC_TR_VAL     0x000002E0 /* Write refresh rate */
  75 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
  76 /*
  77  * Size of malloc() pool
  78  */
  79 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 128*1024)
  80 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
  81
  82 #define CONFIG_BAUDRATE 115200
  83
  84 /*
  85  * Hardware drivers
  86  */
  87
  88 /* define one of these to choose the DBGU, USART0  or USART1 as console */
  89 #define CONFIG_DBGU
  90 #undef CONFIG_USART0
  91 #undef CONFIG_USART1
  92
  93 #undef  CONFIG_HWFLOW                   /* don't include RTS/CTS flow control support   */
  94
  95 #undef  CONFIG_MODEM_SUPPORT            /* disable modem initialization stuff */
  96
  97 #define CONFIG_BOOTDELAY      3
  98 /* #define CONFIG_ENV_OVERWRITE 1 */
  99
 100
 101 /*
 102  * BOOTP options
 103  */
 104 #define CONFIG_BOOTP_BOOTFILESIZE
 105 #define CONFIG_BOOTP_BOOTPATH
 106 #define CONFIG_BOOTP_GATEWAY
 107 #define CONFIG_BOOTP_HOSTNAME
 108
 109
 110 /*
 111  * Command line configuration.
 112  */
 113 #include <config_cmd_default.h>
 114
 115 #define CONFIG_CMD_DHCP
 116 #define CONFIG_CMD_MII
 117 #define CONFIG_CMD_NAND
 118
 119 #define CONFIG_NAND_LEGACY
 120
 121 #define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND devices           */
 122 #define SECTORSIZE 512
 123
 124 #define ADDR_COLUMN 1
 125 #define ADDR_PAGE 2
 126 #define ADDR_COLUMN_PAGE 3
 127
 128 #define NAND_ChipID_UNKNOWN     0x00
 129 #define NAND_MAX_FLOORS 1
 130 #define NAND_MAX_CHIPS 1
 131
 132 #define AT91_SMART_MEDIA_ALE (1 << 22)  /* our ALE is AD22 */
 133 #define AT91_SMART_MEDIA_CLE (1 << 21)  /* our CLE is AD21 */
 134
 135 #include <asm/arch/AT91RM9200.h>        /* needed for port definitions */
 136 #define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
 137 #define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
 138
 139 #define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
 140
 141 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
 142 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
 143 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
 144 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
 145 /* the following are NOP's in our implementation */
 146 #define NAND_CTL_CLRALE(nandptr)
 147 #define NAND_CTL_SETALE(nandptr)
 148 #define NAND_CTL_CLRCLE(nandptr)
 149 #define NAND_CTL_SETCLE(nandptr)
 150
 151 #define CONFIG_NR_DRAM_BANKS 1
 152 #define PHYS_SDRAM 0x20000000
 153 #define PHYS_SDRAM_SIZE 0x2000000  /* 32 megs */
 154
 155 #define CONFIG_SYS_MEMTEST_START                PHYS_SDRAM
 156 #define CONFIG_SYS_MEMTEST_END                  CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
 157
 158 #define CONFIG_DRIVER_ETHER
 159 #define CONFIG_NET_RETRY_COUNT          20
 160 #define CONFIG_AT91C_USE_RMII
 161
 162 /* AC Characteristics */
 163 /* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
 164 #define DATAFLASH_TCSS  (0xC << 16)
 165 #define DATAFLASH_TCHS  (0x1 << 24)
 166
 167 #define CONFIG_HAS_DATAFLASH            1
 168 #define CONFIG_SYS_SPI_WRITE_TOUT               (5*CONFIG_SYS_HZ)
 169 #define CONFIG_SYS_MAX_DATAFLASH_BANKS          2
 170 #define CONFIG_SYS_MAX_DATAFLASH_PAGES          16384
 171 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000      /* Logical adress for CS0 */
 172 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3     0xD0000000      /* Logical adress for CS3 */
 173
 174 #define PHYS_FLASH_1                    0x10000000
 175 #define PHYS_FLASH_SIZE                 0x200000  /* 2 megs main flash */
 176 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 177 #define CONFIG_SYS_MAX_FLASH_BANKS              1
 178 #define CONFIG_SYS_MAX_FLASH_SECT               256
 179 #define CONFIG_SYS_FLASH_ERASE_TOUT             (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 180 #define CONFIG_SYS_FLASH_WRITE_TOUT             (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 181
 182 #undef  CONFIG_ENV_IS_IN_DATAFLASH
 183
 184 #ifdef CONFIG_ENV_IS_IN_DATAFLASH
 185 #define CONFIG_ENV_OFFSET                       0x20000
 186 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 187 #define CONFIG_ENV_SIZE                 0x2000  /* 0x8000 */
 188 #else
 189 #define CONFIG_ENV_IS_IN_FLASH          1
 190 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 191 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0xe000)  /* between boot.bin and u-boot.bin.gz */
 192 #define CONFIG_ENV_SIZE                 0x2000  /* 0x8000 */
 193 #else
 194 #define CONFIG_ENV_ADDR                 (PHYS_FLASH_1 + 0x60000)  /* after u-boot.bin */
 195 #define CONFIG_ENV_SIZE                 0x10000 /* sectors are 64K here */
 196 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
 197 #endif  /* CONFIG_ENV_IS_IN_DATAFLASH */
 198
 199
 200 #define CONFIG_SYS_LOAD_ADDR            0x21000000  /* default load address */
 201
 202 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 203 #define CONFIG_SYS_BOOT_SIZE            0x6000 /* 24 KBytes */
 204 #define CONFIG_SYS_U_BOOT_BASE          (PHYS_FLASH_1 + 0x10000)
 205 #define CONFIG_SYS_U_BOOT_SIZE          0x10000 /* 64 KBytes */
 206 #else
 207 #define CONFIG_SYS_BOOT_SIZE            0x00 /* 0 KBytes */
 208 #define CONFIG_SYS_U_BOOT_BASE          PHYS_FLASH_1
 209 #define CONFIG_SYS_U_BOOT_SIZE          0x60000 /* 384 KBytes */
 210 #endif  /* CONFIG_SKIP_LOWLEVEL_INIT */
 211
 212 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200, 19200, 38400, 57600, 9600 }
 213
 214 #define CONFIG_SYS_PROMPT               "U-Boot> "      /* Monitor Command Prompt */
 215 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size */
 216 #define CONFIG_SYS_MAXARGS              16              /* max number of command args */
 217 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 218
 219 #define CONFIG_SYS_HZ 1000
 220 #define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2        /* AT91C_TC0_CMR is implicitly set to */
 221                                                 /* AT91C_TC_TIMER_DIV1_CLOCK */
 222
 223 #define CONFIG_STACKSIZE        (32*1024)       /* regular stack */
 224
 225 #ifdef CONFIG_USE_IRQ
 226 #error CONFIG_USE_IRQ not supported
 227 #endif
 228
 229 #endif