include/configs/atstk1002.h

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * Configuration settings for the ATSTK1002 CPU daughterboard
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 #define CONFIG_AVR32                    1
  28 #define CONFIG_AT32AP                   1
  29 #define CONFIG_AT32AP7000               1
  30 #define CONFIG_ATSTK1002                1
  31 #define CONFIG_ATSTK1000                1
  32
  33 #define CONFIG_ATSTK1000_EXT_FLASH      1
  34
  35 /*
  36  * Timer clock frequency. We're using the CPU-internal COUNT register
  37  * for this, so this is equivalent to the CPU core clock frequency
  38  */
  39 #define CFG_HZ                          1000
  40
  41 /*
  42  * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL
  43  * frequency and the peripherals to run at 1/4 the PLL frequency.
  44  */
  45 #define CONFIG_PLL                      1
  46 #define CFG_POWER_MANAGER               1
  47 #define CFG_OSC0_HZ                     20000000
  48 #define CFG_PLL0_DIV                    1
  49 #define CFG_PLL0_MUL                    7
  50 #define CFG_PLL0_SUPPRESS_CYCLES        16
  51 #define CFG_CLKDIV_CPU                  0
  52 #define CFG_CLKDIV_HSB                  1
  53 #define CFG_CLKDIV_PBA                  2
  54 #define CFG_CLKDIV_PBB                  1
  55
  56 /*
  57  * The PLLOPT register controls the PLL like this:
  58  *   icp = PLLOPT<2>
  59  *   ivco = PLLOPT<1:0>
  60  *
  61  * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
  62  */
  63 #define CFG_PLL0_OPT                    0x04
  64
  65 #undef CONFIG_USART0
  66 #define CONFIG_USART1                   1
  67 #undef CONFIG_USART2
  68 #undef CONFIG_USART3
  69
  70 /* User serviceable stuff */
  71 #define CONFIG_DOS_PARTITION            1
  72
  73 #define CONFIG_CMDLINE_TAG              1
  74 #define CONFIG_SETUP_MEMORY_TAGS        1
  75 #define CONFIG_INITRD_TAG               1
  76
  77 #define CONFIG_STACKSIZE                (2048)
  78
  79 #define CONFIG_BAUDRATE                 115200
  80 #define CONFIG_BOOTARGS                                                 \
  81         "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2 fbmem=600k"
  82
  83 #define CONFIG_BOOTCOMMAND                                              \
  84         "fsload; bootm $(fileaddr)"
  85
  86 /*
  87  * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
  88  * data on the serial line may interrupt the boot sequence.
  89  */
  90 #define CONFIG_BOOTDELAY                2
  91 #define CONFIG_AUTOBOOT                 1
  92 #define CONFIG_AUTOBOOT_KEYED           1
  93 #define CONFIG_AUTOBOOT_PROMPT                          \
  94         "Press SPACE to abort autoboot in %d seconds\n"
  95 #define CONFIG_AUTOBOOT_DELAY_STR       "d"
  96 #define CONFIG_AUTOBOOT_STOP_STR        " "
  97
  98 /*
  99  * These are "locally administered ethernet addresses" generated by
 100  * ./tools/gen_eth_addr
 101  *
 102  * After booting the board for the first time, new addresses should be
 103  * generated and assigned to the environment variables "ethaddr" and
 104  * "eth1addr".
 105  */
 106 #define CONFIG_ETHADDR                  "6a:87:71:14:cd:cb"
 107 #define CONFIG_ETH1ADDR                 "ca:f8:15:e6:3e:e6"
 108 #define CONFIG_OVERWRITE_ETHADDR_ONCE   1
 109 #define CONFIG_NET_MULTI                1
 110
 111 /*
 112  * BOOTP options
 113  */
 114 #define CONFIG_BOOTP_SUBNETMASK
 115 #define CONFIG_BOOTP_GATEWAY
 116
 117
 118 /*
 119  * Command line configuration.
 120  */
 121 #include <config_cmd_default.h>
 122
 123 #define CONFIG_CMD_ASKENV
 124 #define CONFIG_CMD_DHCP
 125 #define CONFIG_CMD_EXT2
 126 #define CONFIG_CMD_FAT
 127 #define CONFIG_CMD_JFFS2
 128 #define CONFIG_CMD_MMC
 129 #define CONFIG_CMD_REGINFO
 130
 131 #undef CONFIG_CMD_AUTOSCRIPT
 132 #undef CONFIG_CMD_SETGETDCR
 133 #undef CONFIG_CMD_XIMG
 134
 135 #define CONFIG_ATMEL_USART              1
 136 #define CONFIG_MACB                     1
 137 #define CONFIG_PIO2                     1
 138 #define CFG_NR_PIOS                     5
 139 #define CFG_HSDRAMC                     1
 140 #define CONFIG_MMC                      1
 141
 142 #define CFG_DCACHE_LINESZ               32
 143 #define CFG_ICACHE_LINESZ               32
 144
 145 #define CONFIG_NR_DRAM_BANKS            1
 146
 147 /* External flash on STK1000 */
 148 #if 0
 149 #define CFG_FLASH_CFI                   1
 150 #define CFG_FLASH_CFI_DRIVER            1
 151 #endif
 152
 153 #define CFG_FLASH_BASE                  0x00000000
 154 #define CFG_FLASH_SIZE                  0x800000
 155 #define CFG_MAX_FLASH_BANKS             1
 156 #define CFG_MAX_FLASH_SECT              135
 157
 158 #define CFG_MONITOR_BASE                CFG_FLASH_BASE
 159
 160 #define CFG_INTRAM_BASE                 0x24000000
 161 #define CFG_INTRAM_SIZE                 0x8000
 162
 163 #define CFG_SDRAM_BASE                  0x10000000
 164
 165 #define CFG_ENV_IS_IN_FLASH             1
 166 #define CFG_ENV_SIZE                    65536
 167 #define CFG_ENV_ADDR                    (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
 168
 169 #define CFG_INIT_SP_ADDR                (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
 170
 171 #define CFG_MALLOC_LEN                  (256*1024)
 172 #define CFG_DMA_ALLOC_LEN               (16384)
 173
 174 /* Allow 2MB for the kernel run-time image */
 175 #define CFG_LOAD_ADDR                   (CFG_SDRAM_BASE + 0x00200000)
 176 #define CFG_BOOTPARAMS_LEN              (16 * 1024)
 177
 178 /* Other configuration settings that shouldn't have to change all that often */
 179 #define CFG_PROMPT                      "Uboot> "
 180 #define CFG_CBSIZE                      256
 181 #define CFG_MAXARGS                     8
 182 #define CFG_PBSIZE                      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 183 #define CFG_LONGHELP                    1
 184
 185 #define CFG_MEMTEST_START                                               \
 186         ({ gd->bd->bi_dram[0].start; })
 187 #define CFG_MEMTEST_END                                                 \
 188         ({                                                              \
 189                 gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;     \
 190         })
 191 #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
 192
 193 #endif /* __CONFIG_H */