include/configs/barco.h

   1 /********************************************************************
   2  *
   3  * Unless otherwise specified, Copyright (C) 2004-2005 Barco Control Rooms
   4  *
   5  * $Source: /home/services/cvs/firmware/ppc/u-boot-1.1.2/include/configs/barco.h,v $
   6  * $Revision: 1.2 $
   7  * $Author: mleeman $
   8  * $Date: 2005/02/21 12:48:58 $
   9  *
  10  * Last ChangeLog Entry
  11  * $Log: barco.h,v $
  12  * Revision 1.2  2005/02/21 12:48:58  mleeman
  13  * update of copyright years (feedback wd)
  14  *
  15  * Revision 1.1  2005/02/14 09:29:25  mleeman
  16  * moved barcohydra.h to barco.h
  17  *
  18  * Revision 1.4  2005/02/09 12:56:23  mleeman
  19  * add generic header to track changes in sources
  20  *
  21  *
  22  *******************************************************************/
  23
  24 /*
  25  * (C) Copyright 2001, 2002
  26  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  27  *
  28  * See file CREDITS for list of people who contributed to this
  29  * project.
  30  *
  31  * This program is free software; you can redistribute it and/or
  32  * modify it under the terms of the GNU General Public License as
  33  * published by the Free Software Foundation; either version 2 of
  34  * the License, or (at your option) any later version.
  35  *
  36  * This program is distributed in the hope that it will be useful,
  37  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  38  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  39  * GNU General Public License for more details.
  40  *
  41  * You should have received a copy of the GNU General Public License
  42  * along with this program; if not, write to the Free Software
  43  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  44  * MA 02111-1307 USA
  45  */
  46
  47 /* ------------------------------------------------------------------------- */
  48
  49 /*
  50  * board/config.h - configuration options, board specific
  51  */
  52
  53 #ifndef __CONFIG_H
  54 #define __CONFIG_H
  55
  56 /*
  57  * High Level Configuration Options
  58  * (easy to change)
  59  */
  60
  61 #define CONFIG_MPC824X          1
  62 #define CONFIG_MPC8245          1
  63 #define CONFIG_BARCOBCD_STREAMING       1
  64
  65 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  66
  67 #undef USE_DINK32
  68
  69 #define CONFIG_CONS_INDEX     3               /* set to '3' for on-chip DUART */
  70 #define CONFIG_BAUDRATE         9600
  71 #define CONFIG_DRAM_SPEED       100             /* MHz                          */
  72
  73 #define CONFIG_BOOTARGS "mem=32M"
  74
  75
  76 /*
  77  * BOOTP options
  78  */
  79 #define CONFIG_BOOTP_SUBNETMASK
  80 #define CONFIG_BOOTP_GATEWAY
  81 #define CONFIG_BOOTP_HOSTNAME
  82 #define CONFIG_BOOTP_BOOTPATH
  83 #define CONFIG_BOOTP_BOOTFILESIZE
  84 #define CONFIG_BOOTP_DNS
  85
  86
  87 /*
  88  * Command line configuration.
  89  */
  90 #include <config_cmd_default.h>
  91
  92 #define CONFIG_CMD_ELF
  93 #define CONFIG_CMD_I2C
  94 #define CONFIG_CMD_EEPROM
  95 #define CONFIG_CMD_PCI
  96
  97 #undef CONFIG_CMD_NET
  98
  99
 100 #define CONFIG_HUSH_PARSER      1 /* use "hush" command parser */
 101 #define CONFIG_BOOTDELAY        1
 102 #define CONFIG_BOOTCOMMAND      "boot_default"
 103
 104 /*
 105  * Miscellaneous configurable options
 106  */
 107 #define CONFIG_SYS_LONGHELP             1               /* undef to save memory         */
 108 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt       */
 109 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 110 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size    */
 111 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 112 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 113 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address         */
 114 #define CONFIG_SYS_HZ                   1000            /* decrementer freq: 1 ms ticks */
 115
 116
 117 /*-----------------------------------------------------------------------
 118  * PCI stuff
 119  *-----------------------------------------------------------------------
 120  */
 121 #define CONFIG_PCI                              /* include pci support          */
 122 #undef CONFIG_PCI_PNP
 123
 124 #define PCI_ENET0_IOADDR        0x80000000
 125 #define PCI_ENET0_MEMADDR       0x80000000
 126 #define PCI_ENET1_IOADDR        0x81000000
 127 #define PCI_ENET1_MEMADDR       0x81000000
 128
 129
 130 /*-----------------------------------------------------------------------
 131  * Start addresses for the final memory configuration
 132  * (Set up by the startup code)
 133  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 134  */
 135 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 136 #define CONFIG_SYS_MAX_RAM_SIZE 0x02000000
 137
 138 #define CONFIG_LOGBUFFER
 139 #ifdef  CONFIG_LOGBUFFER
 140 #define CONFIG_SYS_STDOUT_ADDR          0x1FFC000
 141 #define CONFIG_SYS_POST_WORD_ADDR       \
 142                 (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE - 4)
 143 #else
 144 #define CONFIG_SYS_STDOUT_ADDR          0x2B9000
 145 #endif
 146
 147 #define CONFIG_SYS_RESET_ADDRESS        0xFFF00100
 148
 149 #if defined (USE_DINK32)
 150 #define CONFIG_SYS_MONITOR_LEN          0x00030000
 151 #define CONFIG_SYS_MONITOR_BASE 0x00090000
 152 #define CONFIG_SYS_RAMBOOT              1
 153 #define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 154 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000
 155 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 156 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 157 #else
 158 #undef  CONFIG_SYS_RAMBOOT
 159 #define CONFIG_SYS_MONITOR_LEN          0x00030000
 160 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 161
 162
 163 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
 164 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000
 165 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 166
 167 #endif
 168
 169 #define CONFIG_SYS_FLASH_BASE           0xFFF00000
 170 #define CONFIG_SYS_FLASH_SIZE           (8 * 1024 * 1024)       /* Unity has onboard 1MByte flash */
 171 #define CONFIG_ENV_IS_IN_FLASH  1
 172 #define CONFIG_ENV_OFFSET               0x000047A4      /* Offset of Environment Sector */
 173 #define CONFIG_ENV_SIZE         0x00002000      /* Total Size of Environment Sector */
 174 /* #define ENV_CRC              0x8BF6F24B      XXX - FIXME: gets defined automatically */
 175
 176 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 512 kB for malloc()  */
 177
 178 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest works on             */
 179 #define CONFIG_SYS_MEMTEST_END          0x04000000      /* 0 ... 32 MB in DRAM          */
 180
 181 #define CONFIG_SYS_EUMB_ADDR            0xFDF00000
 182
 183 #define CONFIG_SYS_FLASH_RANGE_BASE     0xFFC00000      /* flash memory address range   */
 184 #define CONFIG_SYS_FLASH_RANGE_SIZE     0x00400000
 185 #define FLASH_BASE0_PRELIM      0xFFF00000      /* sandpoint flash              */
 186 #define FLASH_BASE1_PRELIM      0xFF000000      /* PMC onboard flash            */
 187
 188 /*
 189  * select i2c support configuration
 190  *
 191  * Supported configurations are {none, software, hardware} drivers.
 192  * If the software driver is chosen, there are some additional
 193  * configuration items that the driver uses to drive the port pins.
 194  */
 195 #define CONFIG_HARD_I2C         1               /* To enable I2C support        */
 196 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 197 #define CONFIG_SYS_I2C_SPEED            400000          /* I2C speed and slave address  */
 198 #define CONFIG_SYS_I2C_SLAVE            0x7F
 199
 200 #ifdef CONFIG_SOFT_I2C
 201 #error "Soft I2C is not configured properly.  Please review!"
 202 #define I2C_PORT                3               /* Port A=0, B=1, C=2, D=3 */
 203 #define I2C_ACTIVE              (iop->pdir |=  0x00010000)
 204 #define I2C_TRISTATE            (iop->pdir &= ~0x00010000)
 205 #define I2C_READ                ((iop->pdat & 0x00010000) != 0)
 206 #define I2C_SDA(bit)            if(bit) iop->pdat |=  0x00010000; \
 207                                 else    iop->pdat &= ~0x00010000
 208 #define I2C_SCL(bit)            if(bit) iop->pdat |=  0x00020000; \
 209                                 else    iop->pdat &= ~0x00020000
 210 #define I2C_DELAY               udelay(5)       /* 1/4 I2C clock duration */
 211 #endif /* CONFIG_SOFT_I2C */
 212
 213 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57            /* EEPROM IS24C02               */
 214 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1               /* Bytes of address             */
 215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
 217
 218 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 219 #define CONFIG_SYS_FLASH_BANKS          { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
 220 #define CONFIG_SYS_DBUS_SIZE2           1
 221
 222 /*-----------------------------------------------------------------------
 223  * Definitions for initial stack pointer and data area (in DPRAM)
 224  */
 225
 226
 227  /*
 228  * NS16550 Configuration (internal DUART)
 229  */
 230  /*
 231  * Low Level Configuration Settings
 232  * (address mappings, register initial values, etc.)
 233  * You should know what you are doing if you make changes here.
 234  */
 235
 236 #define CONFIG_SYS_CLK_FREQ  33333333   /* external frequency to pll */
 237
 238 #define CONFIG_SYS_ROMNAL               0x0F    /*rom/flash next access time            */
 239 #define CONFIG_SYS_ROMFAL               0x1E    /*rom/flash access time                 */
 240
 241 #define CONFIG_SYS_REFINT       0x8F    /* no of clock cycles between CBR refresh cycles */
 242
 243 /* the following are for SDRAM only*/
 244 #define CONFIG_SYS_BSTOPRE      0x25C   /* Burst To Precharge, sets open page interval */
 245 #define CONFIG_SYS_REFREC               8       /* Refresh to activate interval         */
 246 #define CONFIG_SYS_RDLAT                4       /* data latency from read command       */
 247 #define CONFIG_SYS_PRETOACT             3       /* Precharge to activate interval       */
 248 #define CONFIG_SYS_ACTTOPRE             5       /* Activate to Precharge interval       */
 249 #define CONFIG_SYS_ACTORW               2       /* Activate to R/W                      */
 250 #define CONFIG_SYS_SDMODE_CAS_LAT       3       /* SDMODE CAS latency                   */
 251 #define CONFIG_SYS_SDMODE_WRAP          0       /* SDMODE wrap type                     */
 252
 253 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER   1
 254 #define CONFIG_SYS_EXTROM 0
 255 #define CONFIG_SYS_REGDIMM 0
 256
 257
 258 /* memory bank settings*/
 259 /*
 260  * only bits 20-29 are actually used from these vales to set the
 261  * start/end address the upper two bits will be 0, and the lower 20
 262  * bits will be set to 0x00000 for a start address, or 0xfffff for an
 263  * end address
 264  */
 265 #define CONFIG_SYS_BANK0_START          0x00000000
 266 #define CONFIG_SYS_BANK0_END            0x01FFFFFF
 267 #define CONFIG_SYS_BANK0_ENABLE 1
 268 #define CONFIG_SYS_BANK1_START          0x02000000
 269 #define CONFIG_SYS_BANK1_END            0x02ffffff
 270 #define CONFIG_SYS_BANK1_ENABLE 0
 271 #define CONFIG_SYS_BANK2_START          0x03f00000
 272 #define CONFIG_SYS_BANK2_END            0x03ffffff
 273 #define CONFIG_SYS_BANK2_ENABLE 0
 274 #define CONFIG_SYS_BANK3_START          0x04000000
 275 #define CONFIG_SYS_BANK3_END            0x04ffffff
 276 #define CONFIG_SYS_BANK3_ENABLE 0
 277 #define CONFIG_SYS_BANK4_START          0x05000000
 278 #define CONFIG_SYS_BANK4_END            0x05FFFFFF
 279 #define CONFIG_SYS_BANK4_ENABLE 0
 280 #define CONFIG_SYS_BANK5_START          0x06000000
 281 #define CONFIG_SYS_BANK5_END            0x06FFFFFF
 282 #define CONFIG_SYS_BANK5_ENABLE 0
 283 #define CONFIG_SYS_BANK6_START          0x07000000
 284 #define CONFIG_SYS_BANK6_END            0x07FFFFFF
 285 #define CONFIG_SYS_BANK6_ENABLE 0
 286 #define CONFIG_SYS_BANK7_START          0x08000000
 287 #define CONFIG_SYS_BANK7_END            0x08FFFFFF
 288 #define CONFIG_SYS_BANK7_ENABLE 0
 289 /*
 290  * Memory bank enable bitmask, specifying which of the banks defined above
 291  are actually present. MSB is for bank #7, LSB is for bank #0.
 292  */
 293 #define CONFIG_SYS_BANK_ENABLE          0x01
 294
 295 #define CONFIG_SYS_ODCR         0xff    /* configures line driver impedances,   */
 296                                         /* see 8240 book for bit definitions    */
 297 #define CONFIG_SYS_PGMAX                0x32    /* how long the 8240 retains the        */
 298                                         /* currently accessed page in memory    */
 299                                         /* see 8240 book for details            */
 300
 301 /* SDRAM 0 - 256MB */
 302 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 303 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 304
 305 /* stack in DCACHE @ 1GB (no backing mem) */
 306 #if defined(USE_DINK32)
 307 #define CONFIG_SYS_IBAT1L       (0x40000000 | BATL_PP_00 )
 308 #define CONFIG_SYS_IBAT1U       (0x40000000 | BATU_BL_128K )
 309 #else
 310 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 311 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 312 #endif
 313
 314 /* PCI memory */
 315 #define CONFIG_SYS_IBAT2L       (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 316 #define CONFIG_SYS_IBAT2U       (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 317
 318 /* Flash, config addrs, etc */
 319 #define CONFIG_SYS_IBAT3L       (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 320 #define CONFIG_SYS_IBAT3U       (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 321
 322 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 323 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 324 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 325 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 326 #define CONFIG_SYS_DBAT2L       CONFIG_SYS_IBAT2L
 327 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 328 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 329 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 330
 331 /*
 332  * For booting Linux, the board info and command line data
 333  * have to be in the first 8 MB of memory, since this is
 334  * the maximum mapped by the Linux kernel during initialization.
 335  */
 336 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 337 /*-----------------------------------------------------------------------
 338  * FLASH organization
 339  */
 340 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 341 #define CONFIG_SYS_MAX_FLASH_SECT       20      /* max number of sectors on one chip    */
 342
 343 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 344 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 345
 346 #define CONFIG_SYS_FLASH_CHECKSUM
 347
 348 /*-----------------------------------------------------------------------
 349  * Cache Configuration
 350  */
 351 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8240 CPU                      */
 352 #if defined(CONFIG_CMD_KGDB)
 353 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 354 #endif
 355
 356 /* values according to the manual */
 357
 358 #define CONFIG_DRAM_50MHZ       1
 359 #define CONFIG_SDRAM_50MHZ
 360
 361 #define CONFIG_DISK_SPINUP_TIME 1000000
 362
 363
 364 #endif  /* __CONFIG_H */