include/configs/cerf250.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * Configuation settings for the CERF250 board.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_PXA250           1       /* This is an PXA250 CPU    */
  38 #define CONFIG_CERF250          1       /* on Cerf PXA Board        */
  39 #define BOARD_LATE_INIT         1
  40 #define CONFIG_BAUDRATE         38400
  41 #define CONFIG_SYS_TEXT_BASE    0x0
  42
  43 #undef  CONFIG_USE_IRQ                  /* we don't need IRQ/FIQ stuff */
  44
  45 /* we will never enable dcache, because we have to setup MMU first */
  46 #define CONFIG_SYS_NO_DCACHE
  47
  48 /*
  49  * Size of malloc() pool
  50  */
  51 #define CONFIG_SYS_MALLOC_LEN       (CONFIG_ENV_SIZE + 128*1024)
  52
  53 /*
  54  * Hardware drivers
  55  */
  56 #define CONFIG_NET_MULTI
  57 #define CONFIG_SMC91111
  58 #define CONFIG_SMC91111_BASE 0x04000300
  59 #define CONFIG_SMC_USE_32_BIT
  60
  61 /*
  62  * select serial console configuration
  63  */
  64 #define CONFIG_PXA_SERIAL
  65 #define CONFIG_FFUART        1  /* we use FFUART on CERF PXA */
  66
  67 /* allow to overwrite serial and ethaddr */
  68 #define CONFIG_ENV_OVERWRITE
  69
  70 /*
  71  * BOOTP options
  72  */
  73 #define CONFIG_BOOTP_BOOTFILESIZE
  74 #define CONFIG_BOOTP_BOOTPATH
  75 #define CONFIG_BOOTP_GATEWAY
  76 #define CONFIG_BOOTP_HOSTNAME
  77
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84
  85 #define CONFIG_BOOTDELAY        3
  86 #define CONFIG_ETHADDR          00:D0:CA:F1:3C:D2
  87 #define CONFIG_NETMASK          255.255.255.0
  88 #define CONFIG_IPADDR           192.168.0.5
  89 #define CONFIG_SERVERIP         192.168.0.2
  90 #define CONFIG_BOOTCOMMAND      "bootm 0xC0000"
  91 #define CONFIG_BOOTARGS         "root=/dev/mtdblock3 rootfstype=jffs2 console=ttyS0,38400"
  92 #define CONFIG_CMDLINE_TAG
  93
  94 #if defined(CONFIG_CMD_KGDB)
  95 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
  96 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
  97 #endif
  98
  99 /*
 100  * Miscellaneous configurable options
 101  */
 102 #define CONFIG_SYS_HUSH_PARSER          1
 103 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 104
 105 #define CONFIG_SYS_LONGHELP                                     /* undef to save memory         */
 106 #ifdef CONFIG_SYS_HUSH_PARSER
 107 #define CONFIG_SYS_PROMPT                       "uboot$ "       /* Monitor Command Prompt */
 108 #else
 109 #define CONFIG_SYS_PROMPT                       "=> "           /* Monitor Command Prompt */
 110 #endif
 111 #define CONFIG_SYS_CBSIZE                       256                     /* Console I/O Buffer Size      */
 112 #define CONFIG_SYS_PBSIZE                       (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 113                                                                                 /* Print Buffer Size */
 114 #define CONFIG_SYS_MAXARGS                      16                      /* max number of command args   */
 115 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 116 #define CONFIG_SYS_DEVICE_NULLDEV       1
 117
 118 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on     */
 119 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM   */
 120
 121 #define CONFIG_SYS_LOAD_ADDR            0xa2000000      /* default load address */
 122
 123 #define CONFIG_SYS_HZ                   1000
 124 #define CONFIG_SYS_CPUSPEED             0x141           /* set core clock to 400/200/100 MHz */
 125
 126 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 127
 128
 129 /*
 130  * Stack sizes
 131  *
 132  * The stack sizes are set up in start.S using the settings below
 133  */
 134 #define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
 135 #ifdef CONFIG_USE_IRQ
 136 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 137 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 138 #endif
 139
 140 /*
 141  * Physical Memory Map
 142  */
 143 #define CONFIG_NR_DRAM_BANKS            1               /* we have 1 bank of DRAM */
 144 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 145 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
 146
 147 #define PHYS_FLASH_1                    0x00000000      /* Flash Bank #1 */
 148 #define PHYS_FLASH_2                    0x04000000      /* Flash Bank #2 */
 149 #define PHYS_FLASH_SIZE                 0x02000000      /* 32 MB */
 150 #define PHYS_FLASH_BANK_SIZE            0x02000000      /* 32 MB Banks */
 151 #define PHYS_FLASH_SECT_SIZE            0x00040000      /* 256 KB sectors (x2) */
 152
 153 #define CONFIG_SYS_DRAM_BASE                    0xa0000000
 154 #define CONFIG_SYS_DRAM_SIZE                    0x04000000
 155
 156 #define CONFIG_SYS_FLASH_BASE                   PHYS_FLASH_1
 157
 158 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 159 #define CONFIG_SYS_INIT_SP_ADDR         (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 160
 161 /*
 162  * GPIO settings
 163  */
 164
 165
 166 #define CONFIG_SYS_GPSR0_VAL            0x00408030
 167 #define CONFIG_SYS_GPSR1_VAL            0x00BFA882
 168 #define CONFIG_SYS_GPSR2_VAL            0x0001C000
 169 #define CONFIG_SYS_GPCR0_VAL            0xC0031100
 170 #define CONFIG_SYS_GPCR1_VAL            0xFC400300
 171 #define CONFIG_SYS_GPCR2_VAL            0x00003FFF
 172 #define CONFIG_SYS_GPDR0_VAL            0xC0439330
 173 #define CONFIG_SYS_GPDR1_VAL            0xFCFFAB82
 174 #define CONFIG_SYS_GPDR2_VAL            0x0001FFFF
 175 #define CONFIG_SYS_GAFR0_L_VAL          0x80000000
 176 #define CONFIG_SYS_GAFR0_U_VAL          0xA5000010
 177 #define CONFIG_SYS_GAFR1_L_VAL          0x60008018
 178 #define CONFIG_SYS_GAFR1_U_VAL          0xAAA5AAAA
 179 #define CONFIG_SYS_GAFR2_L_VAL          0xAAA0000A
 180 #define CONFIG_SYS_GAFR2_U_VAL          0x00000002
 181
 182 #define CONFIG_SYS_PSSR_VAL             0x20
 183
 184 #define CONFIG_SYS_CCCR                 CCCR_L27|CCCR_M2|CCCR_N10
 185 #define CONFIG_SYS_CKEN                 0x0
 186
 187 /*
 188  * Memory settings
 189  */
 190 #define CONFIG_SYS_MSC0_VAL             0x12447FF0
 191 #define CONFIG_SYS_MSC1_VAL             0x12BC5554
 192 #define CONFIG_SYS_MSC2_VAL             0x7FF97FF1
 193 #define CONFIG_SYS_MDCNFG_VAL           0x00001AC9
 194 #define CONFIG_SYS_MDREFR_VAL           0x03CDC017
 195 #define CONFIG_SYS_MDMRS_VAL            0x00000000
 196 #define CONFIG_SYS_FLYCNFG_VAL          0x00000000
 197 #define CONFIG_SYS_SXCNFG_VAL           0x00000000
 198
 199 /*
 200  * PCMCIA and CF Interfaces
 201  */
 202 #define CONFIG_SYS_MECR_VAL             0x00000000
 203 #define CONFIG_SYS_MCMEM0_VAL           0x00010504
 204 #define CONFIG_SYS_MCMEM1_VAL           0x00010504
 205 #define CONFIG_SYS_MCATT0_VAL           0x00010504
 206 #define CONFIG_SYS_MCATT1_VAL           0x00010504
 207 #define CONFIG_SYS_MCIO0_VAL            0x00004715
 208 #define CONFIG_SYS_MCIO1_VAL            0x00004715
 209
 210 #define _LED                    0x08000010      /*check this */
 211 #define LED_BLANK               0x08000040
 212 #define LED_GPIO                0x10
 213
 214 /*
 215  * FLASH and environment organization
 216  */
 217 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 218 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 219
 220 /* timeout values are in ticks */
 221 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 222 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 223
 224 #define CONFIG_SYS_MONITOR_LEN          0x40000         /* 256 KiB */
 225 #define CONFIG_ENV_IS_IN_FLASH  1
 226 #define CONFIG_ENV_ADDR         (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN)
 227 #define CONFIG_ENV_SIZE         0x40000 /* Total Size of Environment Sector     */
 228
 229
 230 #endif  /* __CONFIG_H */