include/configs/cm_t35.h

   1 /*
   2  * (C) Copyright 2011 CompuLab, Ltd.
   3  * Mike Rapoport <mike@compulab.co.il>
   4  * Igor Grinberg <grinberg@compulab.co.il>
   5  *
   6  * Based on omap3_beagle.h
   7  * (C) Copyright 2006-2008
   8  * Texas Instruments.
   9  * Richard Woodruff <r-woodruff2@ti.com>
  10  * Syed Mohammed Khasim <x0khasim@ti.com>
  11  *
  12  * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards
  13  *
  14  * SPDX-License-Identifier:     GPL-2.0+
  15  */
  16
  17 #ifndef __CONFIG_H
  18 #define __CONFIG_H
  19
  20 #define CONFIG_SYS_CACHELINE_SIZE       64
  21
  22 /*
  23  * High Level Configuration Options
  24  */
  25 #define CONFIG_CM_T3X   /* working with CM-T35 and CM-T3730 */
  26
  27 #include <asm/arch/cpu.h>               /* get chip and board defs */
  28 #include <asm/arch/omap.h>
  29
  30 /* Clock Defines */
  31 #define V_OSCK                  26000000        /* Clock output from T2 */
  32 #define V_SCLK                  (V_OSCK >> 1)
  33
  34 #define CONFIG_MISC_INIT_R
  35
  36 #define CONFIG_CMDLINE_TAG              /* enable passing of ATAGs */
  37 #define CONFIG_SETUP_MEMORY_TAGS
  38 #define CONFIG_INITRD_TAG
  39 #define CONFIG_REVISION_TAG
  40 #define CONFIG_SERIAL_TAG
  41
  42 /*
  43  * Size of malloc() pool
  44  */
  45 #define CONFIG_ENV_SIZE         (16 << 10)      /* 16 KiB */
  46                                         /* Sector */
  47 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + (128 << 10))
  48
  49 /*
  50  * Hardware drivers
  51  */
  52
  53 /*
  54  * NS16550 Configuration
  55  */
  56 #define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  57
  58 #define CONFIG_SYS_NS16550_SERIAL
  59 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  60 #define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  61
  62 /*
  63  * select serial console configuration
  64  */
  65 #define CONFIG_CONS_INDEX               3
  66 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  67 #define CONFIG_SERIAL3                  3       /* UART3 */
  68
  69 /* allow to overwrite serial and ethaddr */
  70 #define CONFIG_ENV_OVERWRITE
  71 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  72                                         115200}
  73
  74 /* USB device configuration */
  75 #define CONFIG_USB_DEVICE
  76 #define CONFIG_USB_TTY
  77
  78 /* commands to include */
  79 #define CONFIG_MTD_DEVICE       /* needed for mtdparts commands */
  80 #define CONFIG_MTD_PARTITIONS
  81
  82 #define CONFIG_SYS_I2C
  83 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
  84 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
  85 #define CONFIG_SYS_I2C_EEPROM_BUS       0
  86 #define CONFIG_I2C_MULTI_BUS
  87
  88 /*
  89  * TWL4030
  90  */
  91 #define CONFIG_TWL4030_LED
  92
  93 /*
  94  * Board NAND Info.
  95  */
  96 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
  97                                                         /* to access nand */
  98 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
  99                                                         /* to access nand at */
 100                                                         /* CS0 */
 101 #define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 102                                                         /* devices */
 103
 104 /* Environment information */
 105 #define CONFIG_EXTRA_ENV_SETTINGS \
 106         "loadaddr=0x82000000\0" \
 107         "usbtty=cdc_acm\0" \
 108         "console=ttyO2,115200n8\0" \
 109         "mpurate=500\0" \
 110         "vram=12M\0" \
 111         "dvimode=1024x768MR-16@60\0" \
 112         "defaultdisplay=dvi\0" \
 113         "mmcdev=0\0" \
 114         "mmcroot=/dev/mmcblk0p2 rw\0" \
 115         "mmcrootfstype=ext4 rootwait\0" \
 116         "nandroot=/dev/mtdblock4 rw\0" \
 117         "nandrootfstype=ubifs\0" \
 118         "mmcargs=setenv bootargs console=${console} " \
 119                 "mpurate=${mpurate} " \
 120                 "vram=${vram} " \
 121                 "omapfb.mode=dvi:${dvimode} " \
 122                 "omapdss.def_disp=${defaultdisplay} " \
 123                 "root=${mmcroot} " \
 124                 "rootfstype=${mmcrootfstype}\0" \
 125         "nandargs=setenv bootargs console=${console} " \
 126                 "mpurate=${mpurate} " \
 127                 "vram=${vram} " \
 128                 "omapfb.mode=dvi:${dvimode} " \
 129                 "omapdss.def_disp=${defaultdisplay} " \
 130                 "root=${nandroot} " \
 131                 "rootfstype=${nandrootfstype}\0" \
 132         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 133         "bootscript=echo Running bootscript from mmc ...; " \
 134                 "source ${loadaddr}\0" \
 135         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 136         "mmcboot=echo Booting from mmc ...; " \
 137                 "run mmcargs; " \
 138                 "bootm ${loadaddr}\0" \
 139         "nandboot=echo Booting from nand ...; " \
 140                 "run nandargs; " \
 141                 "nand read ${loadaddr} 2a0000 400000; " \
 142                 "bootm ${loadaddr}\0" \
 143
 144 #define CONFIG_BOOTCOMMAND \
 145         "mmc dev ${mmcdev}; if mmc rescan; then " \
 146                 "if run loadbootscript; then " \
 147                         "run bootscript; " \
 148                 "else " \
 149                         "if run loaduimage; then " \
 150                                 "run mmcboot; " \
 151                         "else run nandboot; " \
 152                         "fi; " \
 153                 "fi; " \
 154         "else run nandboot; fi"
 155
 156 /*
 157  * Miscellaneous configurable options
 158  */
 159 #define CONFIG_AUTO_COMPLETE
 160 #define CONFIG_CMDLINE_EDITING
 161 #define CONFIG_TIMESTAMP
 162 #define CONFIG_SYS_AUTOLOAD             "no"
 163 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 164
 165 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 166                                                                 /* works on */
 167 #define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 168                                         0x01F00000) /* 31MB */
 169
 170 #define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 171                                                         /* load address */
 172
 173 /*
 174  * OMAP3 has 12 GP timers, they can be driven by the system clock
 175  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 176  * This rate is divided by a local divisor.
 177  */
 178 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 179 #define CONFIG_SYS_PTV                  2       /* Divisor: 2^(PTV+1) => 8 */
 180
 181 /*-----------------------------------------------------------------------
 182  * Physical Memory Map
 183  */
 184 #define CONFIG_NR_DRAM_BANKS    1       /* CS1 is never populated */
 185 #define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 186
 187 /*-----------------------------------------------------------------------
 188  * FLASH and environment organization
 189  */
 190
 191 /* **** PISMO SUPPORT *** */
 192 /* Monitor at start of flash */
 193 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 194 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 195
 196 #define CONFIG_ENV_OFFSET               0x260000
 197 #define CONFIG_ENV_ADDR                 0x260000
 198
 199 /* additions for new relocation code, must be added to all boards */
 200 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 201 #define CONFIG_SYS_INIT_RAM_ADDR        0x4020f800
 202 #define CONFIG_SYS_INIT_RAM_SIZE        0x800
 203 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR +     \
 204                                          CONFIG_SYS_INIT_RAM_SIZE -     \
 205                                          GENERATED_GBL_DATA_SIZE)
 206
 207 /* Status LED */
 208 #define GREEN_LED_GPIO                  186 /* CM-T35 Green LED is GPIO186 */
 209
 210 #define CONFIG_SPLASHIMAGE_GUARD
 211
 212 /* Display Configuration */
 213 #define CONFIG_VIDEO_OMAP3
 214 #define LCD_BPP         LCD_COLOR16
 215
 216 #define CONFIG_SPLASH_SCREEN
 217 #define CONFIG_SPLASH_SOURCE
 218 #define CONFIG_BMP_16BPP
 219 #define CONFIG_SCF0403_LCD
 220
 221 /* Defines for SPL */
 222 #define CONFIG_SPL_FRAMEWORK
 223
 224 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION      1
 225 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
 226
 227 #define CONFIG_SPL_NAND_BASE
 228 #define CONFIG_SPL_NAND_DRIVERS
 229 #define CONFIG_SPL_NAND_ECC
 230
 231 /* NAND boot config */
 232 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 233 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 234 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 235 #define CONFIG_SYS_NAND_OOBSIZE         64
 236 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 237 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   NAND_LARGE_BADBLOCK_POS
 238 /*
 239  * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
 240  * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
 241  */
 242 #define CONFIG_SYS_NAND_ECCPOS          { 1, 2, 3, 4, 5, 6, 7, 8, 9, \
 243                                          10, 11, 12 }
 244 #define CONFIG_SYS_NAND_ECCSIZE         512
 245 #define CONFIG_SYS_NAND_ECCBYTES        3
 246 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 247
 248 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
 249 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 250
 251 #define CONFIG_SPL_TEXT_BASE            0x40200800
 252 #define CONFIG_SPL_MAX_SIZE             (SRAM_SCRATCH_SPACE_ADDR - \
 253                                          CONFIG_SPL_TEXT_BASE)
 254
 255 /*
 256  * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
 257  * older x-loader implementations. And move the BSS area so that it
 258  * doesn't overlap with TEXT_BASE.
 259  */
 260 #define CONFIG_SYS_TEXT_BASE            0x80008000
 261 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 262 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000         /* 512 KB */
 263
 264 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
 265 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 266
 267 /* EEPROM */
 268 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 269 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 270 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 271 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 272 #define CONFIG_SYS_EEPROM_SIZE                  256
 273
 274 #endif /* __CONFIG_H */