include/configs/cogent_mpc8xx.h

   1 /*
   2  * (C) Copyright 2000-2010
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * Config header file for Cogent platform using an MPC8xx CPU module
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC860           1       /* This is an MPC860 CPU        */
  21 #define CONFIG_COGENT           1       /* using Cogent Modular Architecture */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  24
  25 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()            */
  26 #define CONFIG_MISC_INIT_R              /* Use misc_init_r()            */
  27
  28 /* Cogent Modular Architecture options */
  29 #define CONFIG_CMA286_60_OLD    1       /* ...on an old CMA286-60 CPU module */
  30 #define CONFIG_CMA102           1       /* ...on a CMA102 motherboard   */
  31 #define CONFIG_CMA302           1       /* ...with a CMA302 flash I/O module */
  32
  33 /* serial console configuration */
  34 #undef  CONFIG_8xx_CONS_SMC1
  35 #undef  CONFIG_8xx_CONS_SMC2
  36 #define CONFIG_8xx_CONS_NONE    /* not on 8xx serial ports (eg on cogent m/b) */
  37
  38 #if defined(CONFIG_CMA286_60_OLD)
  39 #define CONFIG_8xx_GCLK_FREQ    33333000 /* define if cant use get_gclk_freq */
  40 #endif
  41
  42 #define CONFIG_BAUDRATE         230400
  43
  44 #define CONFIG_HARD_I2C         /* I2C with hardware support */
  45 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
  46 #define CONFIG_SYS_I2C_SLAVE            0x7F
  47
  48
  49 /*
  50  * BOOTP options
  51  */
  52 #define CONFIG_BOOTP_BOOTFILESIZE
  53 #define CONFIG_BOOTP_BOOTPATH
  54 #define CONFIG_BOOTP_GATEWAY
  55 #define CONFIG_BOOTP_HOSTNAME
  56
  57
  58 /*
  59  * Command line configuration.
  60  */
  61 #include <config_cmd_default.h>
  62
  63 #define CONFIG_CMD_KGDB
  64 #define CONFIG_CMD_I2C
  65
  66 #undef CONFIG_CMD_NET
  67 #undef CONFIG_CMD_NFS
  68
  69 #if 0
  70 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  71 #else
  72 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  73 #endif
  74 #define CONFIG_BOOTCOMMAND      "bootm 04080000 04200000" /* autoboot command*/
  75
  76 #define CONFIG_BOOTARGS         "root=/dev/ram rw"
  77
  78 #if defined(CONFIG_CMD_KGDB)
  79 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
  80 #undef  CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
  81 #define CONFIG_KGDB_NONE                /* define if kgdb on something else */
  82 #define CONFIG_KGDB_INDEX       2       /* which SMC/SCC channel for kgdb */
  83 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
  84 #endif
  85
  86 #define CONFIG_WATCHDOG                 /* turn on platform specific watchdog */
  87
  88 /*
  89  * Miscellaneous configurable options
  90  */
  91 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  92 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  93 #if defined(CONFIG_CMD_KGDB)
  94 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  95 #else
  96 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  97 #endif
  98 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  99 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 100 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 101
 102 #define CONFIG_SYS_MEMTEST_START        0x00400000      /* memtest works on     */
 103 #define CONFIG_SYS_MEMTEST_END          0x01c00000      /* 4 ... 28 MB in DRAM  */
 104
 105 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 106
 107 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 108
 109 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
 110
 111 #define CONFIG_SYS_ALLOC_DPRAM
 112
 113 /*
 114  * Low Level Configuration Settings
 115  * (address mappings, register initial values, etc.)
 116  * You should know what you are doing if you make changes here.
 117  */
 118
 119 /*-----------------------------------------------------------------------
 120  * Low Level Cogent settings
 121  * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
 122  * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
 123  * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
 124  * (second 2 for CMA120 only)
 125  */
 126 #define CONFIG_SYS_CMA_MB_BASE          0x00000000      /* base of m/b address space */
 127
 128 #include <configs/cogent_common.h>
 129
 130 #define CONFIG_SYS_CMA_CONS_SERIAL      /* use Cogent motherboard serial for console */
 131 #define CONFIG_CONS_INDEX       1
 132 #define CONFIG_SYS_CMA_LCD_HEARTBEAT    /* define for sec rotator in lcd corner */
 133 #define CONFIG_SHOW_ACTIVITY
 134 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
 135 /*
 136  * flash exists on the motherboard
 137  * set these four according to TOP dipsw:
 138  * TOP on  => ..._FLLOW_...     (boot EPROM space is high so FLASH is low )
 139  * TOP off => ..._FLHIGH_...    (boot EPROM space is low  so FLASH is high)
 140  */
 141 #define CMA_MB_FLASH_EXEC_BASE  CMA_MB_FLLOW_EXEC_BASE
 142 #define CMA_MB_FLASH_EXEC_SIZE  CMA_MB_FLLOW_EXEC_SIZE
 143 #define CMA_MB_FLASH_RDWR_BASE  CMA_MB_FLLOW_RDWR_BASE
 144 #define CMA_MB_FLASH_RDWR_SIZE  CMA_MB_FLLOW_RDWR_SIZE
 145 #endif
 146 #define CMA_MB_FLASH_BASE       CMA_MB_FLASH_EXEC_BASE
 147 #define CMA_MB_FLASH_SIZE       CMA_MB_FLASH_EXEC_SIZE
 148
 149 /*-----------------------------------------------------------------------
 150  * Internal Memory Mapped Register
 151  */
 152 #define CONFIG_SYS_IMMR         0xFF000000
 153
 154 /*-----------------------------------------------------------------------
 155  * Definitions for initial stack pointer and data area (in DPRAM)
 156  */
 157 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 158 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 159 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 160 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 161
 162 /*-----------------------------------------------------------------------
 163  * Start addresses for the final memory configuration
 164  * (Set up by the startup code)
 165  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 166  */
 167 #define CONFIG_SYS_SDRAM_BASE           CMA_MB_RAM_BASE
 168 #ifdef CONFIG_CMA302
 169 #define CONFIG_SYS_FLASH_BASE           CMA_MB_SLOT2_BASE       /* cma302 in slot 2 */
 170 #else
 171 #define CONFIG_SYS_FLASH_BASE           CMA_MB_FLASH_BASE       /* flash on m/b */
 172 #endif
 173 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 174 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 175 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 176
 177 /*
 178  * For booting Linux, the board info and command line data
 179  * have to be in the first 8 MB of memory, since this is
 180  * the maximum mapped by the Linux kernel during initialization.
 181  */
 182 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 183 /*-----------------------------------------------------------------------
 184  * FLASH organization
 185  */
 186 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 187 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max number of sectors on one chip    */
 188
 189 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 190 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 191
 192 #define CONFIG_ENV_IS_IN_FLASH  1
 193 #define CONFIG_ENV_ADDR         CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
 194 #ifdef CONFIG_CMA302
 195 #define CONFIG_ENV_SIZE         0x1000  /* Total Size of Environment Sector     */
 196 #define CONFIG_ENV_SECT_SIZE    (512*1024) /* see README - env sect real size */
 197 #else
 198 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 199 #endif
 200 /*-----------------------------------------------------------------------
 201  * Cache Configuration
 202  */
 203 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 204 #if defined(CONFIG_CMD_KGDB)
 205 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 206 #endif
 207
 208
 209 /*-----------------------------------------------------------------------
 210  * SYPCR - System Protection Control                            11-9
 211  * SYPCR can only be written once after reset!
 212  *-----------------------------------------------------------------------
 213  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 214  */
 215 #if defined(CONFIG_WATCHDOG)
 216 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 217                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 218 #else
 219 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 220 #endif  /* CONFIG_WATCHDOG */
 221
 222 /*-----------------------------------------------------------------------
 223  * SIUMCR - SIU Module Configuration                            11-6
 224  *-----------------------------------------------------------------------
 225  * PCMCIA config., multi-function pin tri-state
 226  */
 227 #define CONFIG_SYS_SIUMCR       (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 228
 229 /*-----------------------------------------------------------------------
 230  * TBSCR - Time Base Status and Control                         11-26
 231  *-----------------------------------------------------------------------
 232  * Clear Reference Interrupt Status, Timebase freezing enabled
 233  */
 234 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 235
 236 /*-----------------------------------------------------------------------
 237  * PISCR - Periodic Interrupt Status and Control                11-31
 238  *-----------------------------------------------------------------------
 239  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 240  */
 241 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 242
 243 /*-----------------------------------------------------------------------
 244  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 245  *-----------------------------------------------------------------------
 246  * Reset PLL lock status sticky bit, timer expired status bit and timer
 247  * interrupt status bit - leave PLL multiplication factor unchanged !
 248  */
 249 #define CONFIG_SYS_PLPRCR       (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 250
 251 /*-----------------------------------------------------------------------
 252  * SCCR - System Clock and reset Control Register               15-27
 253  *-----------------------------------------------------------------------
 254  * Set clock output, timebase and RTC source and divider,
 255  * power management and some other internal clocks
 256  */
 257 #define SCCR_MASK       SCCR_EBDF11
 258 #define CONFIG_SYS_SCCR (SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
 259                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 260                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 261                          SCCR_DFALCD00)
 262
 263 /*-----------------------------------------------------------------------
 264  * PCMCIA stuff
 265  *-----------------------------------------------------------------------
 266  *
 267  */
 268 #define CONFIG_SYS_PCMCIA_MEM_ADDR      (0xE0000000)
 269 #define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 270 #define CONFIG_SYS_PCMCIA_DMA_ADDR      (0xE4000000)
 271 #define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 272 #define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0xE8000000)
 273 #define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 274 #define CONFIG_SYS_PCMCIA_IO_ADDR       (0xEC000000)
 275 #define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 276
 277 /*-----------------------------------------------------------------------
 278  *
 279  *-----------------------------------------------------------------------
 280  *
 281  */
 282 /*#define       CONFIG_SYS_DER  0x2002000F*/
 283 #define CONFIG_SYS_DER  0
 284
 285 #if defined(CONFIG_CMA286_60_OLD)
 286
 287 /*
 288  * Init Memory Controller:
 289  *
 290  * NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings,
 291  * they are actually the final settings for this cpu/board, because the
 292  * flash and RAM are on the motherboard, accessed via the CMAbus, and the
 293  * mappings are pretty much fixed.
 294  *
 295  * (the *_SIZE vars must be a power of 2)
 296  */
 297
 298 #define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE            /* EPROM */
 299 #define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
 300 #define CONFIG_SYS_CMA_CS1_BASE CMA_MB_RAM_BASE         /* RAM + I/O SLOT 1 */
 301 #define CONFIG_SYS_CMA_CS1_SIZE (64 << 20)
 302 #define CONFIG_SYS_CMA_CS2_BASE CMA_MB_SLOT2_BASE       /* I/O SLOTS 2 + 3 */
 303 #define CONFIG_SYS_CMA_CS2_SIZE (64 << 20)
 304 #define CONFIG_SYS_CMA_CS3_BASE CMA_MB_ROMLOW_BASE      /* M/B I/O */
 305 #define CONFIG_SYS_CMA_CS3_SIZE (32 << 20)
 306
 307 /*
 308  * CS0 maps the EPROM on the cpu module
 309  * Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
 310  *
 311  * Note: We must have already transferred control to the final location
 312  * of the EPROM before these are used, because when BR0/OR0 are set, the
 313  * mirror of the eprom at any other addresses will disappear.
 314  */
 315
 316 /* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
 317 #define CONFIG_SYS_BR0_PRELIM   ((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
 318 /* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
 319 #define CONFIG_SYS_OR0_PRELIM   ((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)
 320
 321 /*
 322  * CS1 maps motherboard DRAM and motherboard I/O slot 1
 323  * (each 32Mbyte in size)
 324  */
 325
 326 /* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
 327 #define CONFIG_SYS_BR1_PRELIM   ((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
 328 /* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
 329 #define CONFIG_SYS_OR1_PRELIM   ((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)
 330
 331 /*
 332  * CS2 maps motherboard I/O slots 2 and 3
 333  * (each 32Mbyte in size)
 334  */
 335
 336 /* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
 337 #define CONFIG_SYS_BR2_PRELIM   ((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
 338 /* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
 339 #define CONFIG_SYS_OR2_PRELIM   ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)
 340
 341 /*
 342  * CS3 maps motherboard I/O
 343  * (32Mbyte in size)
 344  */
 345
 346 /* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
 347 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
 348 /* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
 349 #define CONFIG_SYS_OR3_PRELIM   ((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)
 350
 351 #endif
 352 #endif  /* __CONFIG_H */