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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/corenet_ds.h
2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * Corenet DS style board configuration file
29 #include "../board/freescale/common/ics307_clk.h"
31 #ifdef CONFIG_RAMBOOT_PBL
32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
36 /* High Level Configuration Options */
38 #define CONFIG_E500 /* BOOKE e500 family */
39 #define CONFIG_E500MC /* BOOKE e500mc family */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
41 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */
42 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
43 #define CONFIG_MP /* support multiple processors */
45 #ifndef CONFIG_SYS_TEXT_BASE
46 #define CONFIG_SYS_TEXT_BASE 0xeff80000
49 #ifndef CONFIG_RESET_VECTOR_ADDRESS
50 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
55 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
56 #define CONFIG_PCI /* Enable PCI/PCIE */
57 #define CONFIG_PCIE1 /* PCIE controler 1 */
58 #define CONFIG_PCIE2 /* PCIE controler 2 */
59 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
62 #define CONFIG_SYS_SRIO
63 #define CONFIG_SRIO1 /* SRIO port 1 */
64 #define CONFIG_SRIO2 /* SRIO port 2 */
66 #define CONFIG_FSL_LAW /* Use common FSL init code */
68 #define CONFIG_ENV_OVERWRITE
70 #ifdef CONFIG_SYS_NO_FLASH
71 #define CONFIG_ENV_IS_NOWHERE
73 #define CONFIG_FLASH_CFI_DRIVER
74 #define CONFIG_SYS_FLASH_CFI
75 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
78 #if defined(CONFIG_SPIFLASH)
79 #define CONFIG_SYS_EXTRA_ENV_RELOC
80 #define CONFIG_ENV_IS_IN_SPI_FLASH
81 #define CONFIG_ENV_SPI_BUS 0
82 #define CONFIG_ENV_SPI_CS 0
83 #define CONFIG_ENV_SPI_MAX_HZ 10000000
84 #define CONFIG_ENV_SPI_MODE 0
85 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
86 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
87 #define CONFIG_ENV_SECT_SIZE 0x10000
88 #elif defined(CONFIG_SDCARD)
89 #define CONFIG_SYS_EXTRA_ENV_RELOC
90 #define CONFIG_ENV_IS_IN_MMC
91 #define CONFIG_FSL_FIXED_MMC_LOCATION
92 #define CONFIG_SYS_MMC_ENV_DEV 0
93 #define CONFIG_ENV_SIZE 0x2000
94 #define CONFIG_ENV_OFFSET (512 * 1097)
95 #elif defined(CONFIG_NAND)
96 #define CONFIG_SYS_EXTRA_ENV_RELOC
97 #define CONFIG_ENV_IS_IN_NAND
98 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
99 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
100 #elif defined(CONFIG_ENV_IS_NOWHERE)
101 #define CONFIG_ENV_SIZE 0x2000
103 #define CONFIG_ENV_IS_IN_FLASH
104 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
105 #define CONFIG_ENV_SIZE 0x2000
106 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
109 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
112 * These can be toggled for performance analysis, otherwise use default.
114 #define CONFIG_SYS_CACHE_STASHING
115 #define CONFIG_BACKSIDE_L2_CACHE
116 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
117 #define CONFIG_BTB /* toggle branch predition */
118 #define CONFIG_DDR_ECC
119 #ifdef CONFIG_DDR_ECC
120 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
121 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
124 #define CONFIG_ENABLE_36BIT_PHYS
126 #ifdef CONFIG_PHYS_64BIT
127 #define CONFIG_ADDR_MAP
128 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
131 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
132 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
133 #define CONFIG_SYS_MEMTEST_END 0x00400000
134 #define CONFIG_SYS_ALT_MEMTEST
135 #define CONFIG_PANIC_HANG /* do not reset board on panic */
138 * Config the L3 Cache as L3 SRAM
140 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
141 #ifdef CONFIG_PHYS_64BIT
142 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
144 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
146 #define CONFIG_SYS_L3_SIZE (1024 << 10)
147 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
149 #ifdef CONFIG_PHYS_64BIT
150 #define CONFIG_SYS_DCSRBAR 0xf0000000
151 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
155 #define CONFIG_ID_EEPROM
156 #define CONFIG_SYS_I2C_EEPROM_NXID
157 #define CONFIG_SYS_EEPROM_BUS_NUM 0
158 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
159 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
164 #define CONFIG_VERY_BIG_RAM
165 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
166 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
168 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
169 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
171 #define CONFIG_DDR_SPD
172 #define CONFIG_FSL_DDR3
174 #ifdef CONFIG_P3060QDS
175 #define CONFIG_SYS_SPD_BUS_NUM 0
177 #define CONFIG_SYS_SPD_BUS_NUM 1
179 #define SPD_EEPROM_ADDRESS1 0x51
180 #define SPD_EEPROM_ADDRESS2 0x52
181 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
182 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
185 * Local Bus Definitions
188 /* Set the local bus clock 1/8 of platform clock */
189 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
191 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */
192 #ifdef CONFIG_PHYS_64BIT
193 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
195 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
198 #define CONFIG_SYS_FLASH_BR_PRELIM \
199 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
201 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
202 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
204 #define CONFIG_SYS_BR1_PRELIM \
205 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
206 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
208 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
209 #ifdef CONFIG_PHYS_64BIT
210 #define PIXIS_BASE_PHYS 0xfffdf0000ull
212 #define PIXIS_BASE_PHYS PIXIS_BASE
215 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
216 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
218 #define PIXIS_LBMAP_SWITCH 7
219 #define PIXIS_LBMAP_MASK 0xf0
220 #define PIXIS_LBMAP_SHIFT 4
221 #define PIXIS_LBMAP_ALTBANK 0x40
223 #define CONFIG_SYS_FLASH_QUIET_TEST
224 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
226 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
227 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
228 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
229 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
231 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
233 #if defined(CONFIG_RAMBOOT_PBL)
234 #define CONFIG_SYS_RAMBOOT
238 #ifdef CONFIG_NAND_FSL_ELBC
239 #define CONFIG_SYS_NAND_BASE 0xffa00000
240 #ifdef CONFIG_PHYS_64BIT
241 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
243 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
246 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
247 #define CONFIG_SYS_MAX_NAND_DEVICE 1
248 #define CONFIG_MTD_NAND_VERIFY_WRITE
249 #define CONFIG_CMD_NAND
250 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
252 /* NAND flash config */
253 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
254 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
255 | BR_PS_8 /* Port Size = 8 bit */ \
256 | BR_MS_FCM /* MSEL = FCM */ \
258 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
259 | OR_FCM_PGS /* Large Page*/ \
268 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
269 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
270 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
271 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
275 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
276 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
279 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
280 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
281 #endif /* CONFIG_NAND_FSL_ELBC */
283 #define CONFIG_SYS_FLASH_EMPTY_INFO
284 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
285 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
287 #define CONFIG_BOARD_EARLY_INIT_F
288 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
289 #define CONFIG_MISC_INIT_R
291 #define CONFIG_HWCONFIG
293 /* define to use L1 as initial stack */
294 #define CONFIG_L1_INIT_RAM
295 #define CONFIG_SYS_INIT_RAM_LOCK
296 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
297 #ifdef CONFIG_PHYS_64BIT
298 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
299 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
300 /* The assembler doesn't like typecast */
301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
302 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
303 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
309 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
311 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
312 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
314 #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
315 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
317 /* Serial Port - controlled on board with jumper J8
321 #define CONFIG_CONS_INDEX 1
322 #define CONFIG_SYS_NS16550
323 #define CONFIG_SYS_NS16550_SERIAL
324 #define CONFIG_SYS_NS16550_REG_SIZE 1
325 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
327 #define CONFIG_SYS_BAUDRATE_TABLE \
328 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
330 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
331 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
332 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
333 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
335 /* Use the HUSH parser */
336 #define CONFIG_SYS_HUSH_PARSER
337 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
339 /* pass open firmware flat tree */
340 #define CONFIG_OF_LIBFDT
341 #define CONFIG_OF_BOARD_SETUP
342 #define CONFIG_OF_STDOUT_VIA_ALIAS
344 /* new uImage format support */
346 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
349 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
350 #define CONFIG_HARD_I2C /* I2C with hardware support */
351 #define CONFIG_I2C_MULTI_BUS
352 #define CONFIG_I2C_CMD_TREE
353 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
354 #define CONFIG_SYS_I2C_SLAVE 0x7F
355 #define CONFIG_SYS_I2C_OFFSET 0x118000
356 #define CONFIG_SYS_I2C2_OFFSET 0x118100
361 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
362 #ifdef CONFIG_PHYS_64BIT
363 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
365 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
367 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
369 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
370 #ifdef CONFIG_PHYS_64BIT
371 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
373 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
375 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
378 * eSPI - Enhanced SPI
380 #define CONFIG_FSL_ESPI
381 #define CONFIG_SPI_FLASH
382 #define CONFIG_SPI_FLASH_SPANSION
383 #define CONFIG_CMD_SF
384 #define CONFIG_SF_DEFAULT_SPEED 10000000
385 #define CONFIG_SF_DEFAULT_MODE 0
389 * Memory space is mapped 1-1, but I/O space must start from 0.
392 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
393 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
394 #ifdef CONFIG_PHYS_64BIT
395 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
396 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
398 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
399 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
401 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
402 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
403 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
404 #ifdef CONFIG_PHYS_64BIT
405 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
407 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
409 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
411 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
412 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
413 #ifdef CONFIG_PHYS_64BIT
414 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
415 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
417 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
418 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
420 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
421 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
422 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
423 #ifdef CONFIG_PHYS_64BIT
424 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
426 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
428 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
430 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
431 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
432 #ifdef CONFIG_PHYS_64BIT
433 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
434 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
436 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
437 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
439 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
440 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
441 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
442 #ifdef CONFIG_PHYS_64BIT
443 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
445 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
447 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
449 /* controller 4, Base address 203000 */
450 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
451 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
452 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
453 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
454 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
455 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
458 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
459 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
460 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
461 #ifdef CONFIG_PHYS_64BIT
462 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
464 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
466 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
467 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
468 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
469 #ifdef CONFIG_PHYS_64BIT
470 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
472 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
474 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
476 #define CONFIG_SYS_DPAA_FMAN
477 #define CONFIG_SYS_DPAA_PME
478 /* Default address of microcode for the Linux Fman driver */
479 #if defined(CONFIG_SPIFLASH)
481 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
482 * env, so we got 0x110000.
484 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
485 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000
486 #elif defined(CONFIG_SDCARD)
488 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
489 * about 545KB (1089 blocks), Env is stored after the image, and the env size is
490 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
492 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
493 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130)
494 #elif defined(CONFIG_NAND)
495 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
496 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
498 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
499 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
501 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
502 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
504 #ifdef CONFIG_SYS_DPAA_FMAN
505 #define CONFIG_FMAN_ENET
506 #define CONFIG_PHYLIB_10G
507 #define CONFIG_PHY_VITESSE
508 #define CONFIG_PHY_TERANETICS
512 #define CONFIG_PCI_PNP /* do pci plug-and-play */
515 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
516 #define CONFIG_DOS_PARTITION
517 #endif /* CONFIG_PCI */
520 #ifdef CONFIG_FSL_SATA_V2
521 #define CONFIG_LIBATA
522 #define CONFIG_FSL_SATA
524 #define CONFIG_SYS_SATA_MAX_DEVICE 2
526 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
527 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
529 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
530 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
533 #define CONFIG_CMD_SATA
534 #define CONFIG_DOS_PARTITION
535 #define CONFIG_CMD_EXT2
538 #ifdef CONFIG_FMAN_ENET
539 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c
540 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d
541 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e
542 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f
543 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4
545 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c
546 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d
547 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e
548 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f
549 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0
551 #define CONFIG_SYS_TBIPA_VALUE 8
552 #define CONFIG_MII /* MII PHY management */
553 #define CONFIG_ETHPRIME "FM1@DTSEC1"
554 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
560 #define CONFIG_LOADS_ECHO /* echo on for serial download */
561 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
564 * Command line configuration.
566 #include <config_cmd_default.h>
568 #define CONFIG_CMD_DHCP
569 #define CONFIG_CMD_ELF
570 #define CONFIG_CMD_ERRATA
571 #define CONFIG_CMD_GREPENV
572 #define CONFIG_CMD_IRQ
573 #define CONFIG_CMD_I2C
574 #define CONFIG_CMD_MII
575 #define CONFIG_CMD_PING
576 #define CONFIG_CMD_SETEXPR
577 #define CONFIG_CMD_REGINFO
580 #define CONFIG_CMD_PCI
581 #define CONFIG_CMD_NET
587 #define CONFIG_CMD_USB
588 #define CONFIG_USB_STORAGE
589 #define CONFIG_USB_EHCI
590 #define CONFIG_USB_EHCI_FSL
591 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
592 #define CONFIG_CMD_EXT2
593 #define CONFIG_HAS_FSL_DR_USB
596 #define CONFIG_FSL_ESDHC
597 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
598 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
599 #define CONFIG_CMD_MMC
600 #define CONFIG_GENERIC_MMC
601 #define CONFIG_CMD_EXT2
602 #define CONFIG_CMD_FAT
603 #define CONFIG_DOS_PARTITION
607 * Miscellaneous configurable options
609 #define CONFIG_SYS_LONGHELP /* undef to save memory */
610 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
611 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
612 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
613 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
614 #ifdef CONFIG_CMD_KGDB
615 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
617 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
619 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
620 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
621 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
622 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
625 * For booting Linux, the board info and command line data
626 * have to be in the first 64 MB of memory, since this is
627 * the maximum mapped by the Linux kernel during initialization.
629 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
630 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
632 #ifdef CONFIG_CMD_KGDB
633 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
634 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
638 * Environment Configuration
640 #define CONFIG_ROOTPATH "/opt/nfsroot"
641 #define CONFIG_BOOTFILE "uImage"
642 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
644 /* default location for tftp and bootm */
645 #define CONFIG_LOADADDR 1000000
647 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
649 #define CONFIG_BAUDRATE 115200
651 #if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS)
652 #define __USB_PHY_TYPE ulpi
654 #define __USB_PHY_TYPE utmi
657 #define CONFIG_EXTRA_ENV_SETTINGS \
658 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
659 "bank_intlv=cs0_cs1;" \
660 "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\
662 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
663 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
664 "tftpflash=tftpboot $loadaddr $uboot && " \
665 "protect off $ubootaddr +$filesize && " \
666 "erase $ubootaddr +$filesize && " \
667 "cp.b $loadaddr $ubootaddr $filesize && " \
668 "protect on $ubootaddr +$filesize && " \
669 "cmp.b $loadaddr $ubootaddr $filesize\0" \
670 "consoledev=ttyS0\0" \
671 "ramdiskaddr=2000000\0" \
672 "ramdiskfile=p4080ds/ramdisk.uboot\0" \
674 "fdtfile=p4080ds/p4080ds.dtb\0" \
678 #define CONFIG_HDBOOT \
679 "setenv bootargs root=/dev/$bdev rw " \
680 "console=$consoledev,$baudrate $othbootargs;" \
681 "tftp $loadaddr $bootfile;" \
682 "tftp $fdtaddr $fdtfile;" \
683 "bootm $loadaddr - $fdtaddr"
685 #define CONFIG_NFSBOOTCOMMAND \
686 "setenv bootargs root=/dev/nfs rw " \
687 "nfsroot=$serverip:$rootpath " \
688 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
689 "console=$consoledev,$baudrate $othbootargs;" \
690 "tftp $loadaddr $bootfile;" \
691 "tftp $fdtaddr $fdtfile;" \
692 "bootm $loadaddr - $fdtaddr"
694 #define CONFIG_RAMBOOTCOMMAND \
695 "setenv bootargs root=/dev/ram rw " \
696 "console=$consoledev,$baudrate $othbootargs;" \
697 "tftp $ramdiskaddr $ramdiskfile;" \
698 "tftp $loadaddr $bootfile;" \
699 "tftp $fdtaddr $fdtfile;" \
700 "bootm $loadaddr $ramdiskaddr $fdtaddr"
702 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
704 #ifdef CONFIG_SECURE_BOOT
705 #include <asm/fsl_secure_boot.h>
708 #endif /* __CONFIG_H */