include/configs/cpci5200.h

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22
  23  */
  24
  25 /*************************************************************************
  26  * (c) 2005 esd gmbh Hannover
  27  *
  28  *
  29  * from IceCube.h file
  30  * by Reinhard Arlt reinhard.arlt@esd-electronics.com
  31  *
  32  *************************************************************************/
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 /*
  38  * High Level Configuration Options
  39  * (easy to change)
  40  */
  41
  42 #define CONFIG_MPC5200          1       /* This is an MPC5xxx CPU */
  43 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  44 #define CONFIG_ICECUBE          1       /* ... on IceCube board   */
  45 #define CONFIG_CPCI5200         1       /* ... on CPCI5200  board */
  46 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM        */
  47
  48 #define CFG_MPC5XXX_CLKIN       33000000        /* ... running at 33.000000MHz */
  49
  50 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH  */
  51 #define BOOTFLAG_WARM           0x02    /* Software reboot           */
  52
  53 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs */
  54 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  55 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value */
  56 #endif
  57
  58 /*
  59  * Serial console configuration
  60  */
  61 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  62 #define CONFIG_BAUDRATE         9600    /* ... at 115200 bps */
  63 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  64
  65 #ifdef CONFIG_MPC5200           /* MPC5100 PCI is not supported yet. */
  66 /*
  67  * PCI Mapping:
  68  * 0x40000000 - 0x4fffffff - PCI Memory
  69  * 0x50000000 - 0x50ffffff - PCI IO Space
  70  */
  71 #if 1
  72 #define CONFIG_PCI              1
  73 #if 1
  74 #define CONFIG_PCI_PNP          1
  75 #endif
  76 #define CONFIG_PCI_SCAN_SHOW    1
  77
  78 #define CONFIG_PCI_MEM_BUS      0x40000000
  79 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  80 #define CONFIG_PCI_MEM_SIZE     0x10000000
  81
  82 #define CONFIG_PCI_IO_BUS       0x50000000
  83 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  84 #define CONFIG_PCI_IO_SIZE      0x01000000
  85 #endif
  86
  87 #define CONFIG_MII
  88 #if 0                           /* test-only !!! */
  89 #define CONFIG_NET_MULTI        1
  90 #define CONFIG_EEPRO100         1
  91 #define CFG_RX_ETH_BUFFER       8       /* use 8 rx buffer on eepro100  */
  92 #define CONFIG_NS8382X          1
  93 #endif
  94
  95 #define ADD_PCI_CMD             CFG_CMD_PCI
  96
  97 #else                           /* MPC5100 */
  98
  99 #define ADD_PCI_CMD             0       /* no CFG_CMD_PCI */
 100
 101 #endif
 102
 103 /* Partitions */
 104 #define CONFIG_MAC_PARTITION
 105 #define CONFIG_DOS_PARTITION
 106
 107 /* USB */
 108 #if 0
 109 #define CONFIG_USB_OHCI
 110 #define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
 111 #define CONFIG_USB_STORAGE
 112 #else
 113 #define ADD_USB_CMD             0
 114 #endif
 115
 116 /*
 117  * Supported commands
 118  */
 119 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | \
 120                                  CFG_CMD_EEPROM | \
 121                                  CFG_CMD_FAT    | \
 122                                  CFG_CMD_IDE    | \
 123                                  CFG_CMD_I2C    | \
 124                                  CFG_CMD_BSP    | \
 125                                  CFG_CMD_ELF    | \
 126                                  CFG_CMD_EXT2   | \
 127                                  CFG_CMD_DATE   | \
 128                                  ADD_PCI_CMD      )
 129
 130 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 131 #include <cmd_confdefs.h>
 132
 133 #if (TEXT_BASE == 0xFF000000)   /* Boot low with 16 MB Flash */
 134 #   define CFG_LOWBOOT          1
 135 #   define CFG_LOWBOOT16        1
 136 #endif
 137 #if (TEXT_BASE == 0xFF800000)   /* Boot low with  8 MB Flash */
 138 #   define CFG_LOWBOOT          1
 139 #   define CFG_LOWBOOT08        1
 140 #endif
 141
 142 /*
 143  * Autobooting
 144  */
 145 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds */
 146
 147 #define CONFIG_PREBOOT  "echo;" \
 148         "echo Welcome to esd CPU CPCI/5200;" \
 149         "echo"
 150
 151 #undef  CONFIG_BOOTARGS
 152
 153 #define CONFIG_EXTRA_ENV_SETTINGS \
 154         "netdev=eth0\0" \
 155         "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
 156         "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
 157         "net_vxworks=phypower 1;sleep 2;tftp ${loadaddr} ${image};run vxworks_args;bootvx\0" \
 158         "vxworks_args=setenv bootargs fec(0,0)${host}:${image} h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script}\0" \
 159         "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=${serverip} e=${ipaddr} g=${gatewayip} u=${user} ${pass} tn=${target} s=${script} o=fec0 \0" \
 160         "loadaddr=01000000\0" \
 161         "serverip=192.168.2.99\0" \
 162         "gatewayip=10.0.0.79\0" \
 163         "user=mu\0" \
 164         "target=cpci5200.esd\0" \
 165         "script=cpci5200.bat\0" \
 166         "image=/tftpboot/vxWorks_cpci5200\0" \
 167         "ipaddr=10.0.13.196\0" \
 168         "netmask=255.255.0.0\0" \
 169         ""
 170
 171 #define CONFIG_BOOTCOMMAND      "run flash_vxworks0"
 172
 173 #if defined(CONFIG_MPC5200)
 174
 175 #define CONFIG_RTC_M48T35A      1       /* ST Electronics M48 timekeeper */
 176 #define CFG_NVRAM_BASE_ADDR     0xfd010000
 177 #define CFG_NVRAM_SIZE          32*1024
 178
 179 /*
 180  * IPB Bus clocking configuration.
 181  */
 182 #undef CFG_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 183 #endif
 184 /*
 185  * I2C configuration
 186  */
 187 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 188 #define CFG_I2C_MODULE          1       /* Select I2C module #1 or #2 */
 189
 190 #define CFG_I2C_SPEED           86000   /* 100 kHz */
 191 #define CFG_I2C_SLAVE           0x7F
 192
 193 /*
 194  * EEPROM configuration
 195  */
 196 #define CFG_I2C_EEPROM_ADDR             0x50    /* 1010000x */
 197 #define CFG_I2C_EEPROM_ADDR_LEN         2
 198 #define CFG_EEPROM_PAGE_WRITE_BITS      5
 199 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  20
 200 #define CFG_I2C_MULTI_EEPROMS           1
 201 /*
 202  * Flash configuration
 203  */
 204
 205 #define CFG_FLASH_CFI           1       /* Flash is CFI conformant           */
 206 #define CFG_FLASH_BASE          0xFE000000
 207 #define CFG_FLASH_SIZE          0x02000000
 208 #define CFG_FLASH_INCREMENT     0x01000000
 209 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x00000000)
 210 #define CFG_MAX_FLASH_BANKS     2       /* max num of memory banks      */
 211 #define CFG_MAX_FLASH_SECT      128
 212
 213 #define CFG_FLASH_PROTECTION    1       /* use hardware protection           */
 214 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)  */
 215
 216 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 217 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 218
 219 /*
 220  * Environment settings
 221  */
 222 #if 1                           /* test-only */
 223 #define CFG_ENV_IS_IN_FLASH     1
 224 #define CFG_ENV_SIZE            0x20000
 225 #define CFG_ENV_SECT_SIZE       0x20000
 226 #define CONFIG_ENV_OVERWRITE    1
 227 #else
 228 #define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
 229 #define CFG_ENV_OFFSET          0x0000  /* environment starts at the beginning of the EEPROM */
 230 #define CFG_ENV_SIZE            0x0400  /* 8192 bytes may be used for env vars */
 231                                    /* total size of a CAT24WC32 is 8192 bytes */
 232 #define CONFIG_ENV_OVERWRITE    1
 233 #endif
 234
 235 /*
 236  * Memory map
 237  */
 238 #define CFG_MBAR                0xF0000000
 239 #define CFG_SDRAM_BASE          0x00000000
 240 #define CFG_DEFAULT_MBAR        0x80000000
 241
 242 /* Use SRAM until RAM will be available */
 243 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 244 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 245
 246 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 247 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 248 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 249
 250 #define CFG_MONITOR_BASE    TEXT_BASE
 251 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 252 #   define CFG_RAMBOOT          1
 253 #endif
 254
 255 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 256 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 257 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 258
 259 /*
 260  * Ethernet configuration
 261  */
 262 #define CONFIG_MPC5xxx_FEC      1
 263 /*
 264  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 265  */
 266 /* #define CONFIG_FEC_10MBIT 1 */
 267 #define CONFIG_PHY_ADDR         0x00
 268 #define CONFIG_UDP_CHECKSUM     1
 269
 270 /*
 271  * GPIO configuration
 272  */
 273 #define CFG_GPS_PORT_CONFIG     0x01052444
 274
 275 /*
 276  * Miscellaneous configurable options
 277  */
 278 #define CFG_LONGHELP            /* undef to save memory     */
 279 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 280 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 281 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 282 #else
 283 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 284 #endif
 285 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 286 #define CFG_MAXARGS             16      /* max number of command args   */
 287 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 288
 289 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 290 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 291
 292 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 293
 294 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 295
 296 #define CFG_VXWORKS_MAC_PTR     0x00000000      /* Pass Ethernet MAC to VxWorks */
 297
 298 /*
 299  * Various low-level settings
 300  */
 301 #if defined(CONFIG_MPC5200)
 302 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 303 #define CFG_HID0_FINAL          HID0_ICE
 304 #else
 305 #define CFG_HID0_INIT           0
 306 #define CFG_HID0_FINAL          0
 307 #endif
 308
 309 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 310 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 311 #define CFG_BOOTCS_CFG          0x0004DD00
 312
 313 #define CFG_CS0_START           CFG_FLASH_BASE
 314 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 315
 316 #define CFG_CS1_START           0xfd000000
 317 #define CFG_CS1_SIZE            0x00010000
 318 #define CFG_CS1_CFG             0x10101410
 319
 320 #define CFG_CS3_START           0xfd010000
 321 #define CFG_CS3_SIZE            0x00010000
 322 #define CFG_CS3_CFG             0x10109410
 323
 324 #define CFG_CS_BURST            0x00000000
 325 #define CFG_CS_DEADCYCLE        0x33333333
 326
 327 #define CFG_RESET_ADDRESS       0xff000000
 328
 329 /*-----------------------------------------------------------------------
 330  * USB stuff
 331  *-----------------------------------------------------------------------
 332  */
 333 #define CONFIG_USB_CLOCK        0x0001BBBB
 334 #define CONFIG_USB_CONFIG       0x00001000
 335
 336 /*-----------------------------------------------------------------------
 337  * IDE/ATA stuff Supports IDE harddisk
 338  *-----------------------------------------------------------------------
 339  */
 340
 341 #undef  CONFIG_IDE_8xx_PCCARD   /* Use IDE with PC Card Adapter */
 342
 343 #undef  CONFIG_IDE_8xx_DIRECT   /* Direct IDE    not supported  */
 344 #undef  CONFIG_IDE_LED          /* LED   for ide not supported  */
 345
 346 #define CONFIG_IDE_RESET        /* reset for ide supported      */
 347 #define CONFIG_IDE_PREINIT
 348
 349 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 350 #define CFG_IDE_MAXDEVICE       1       /* max. 1 drive per IDE bus     */
 351
 352 #define CFG_ATA_IDE0_OFFSET     0x0000
 353
 354 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 355
 356 /* Offset for data I/O                  */
 357 #define CFG_ATA_DATA_OFFSET     (0x0060)
 358
 359 /* Offset for normal register accesses  */
 360 #define CFG_ATA_REG_OFFSET      (CFG_ATA_DATA_OFFSET)
 361
 362 /* Offset for alternate registers       */
 363 #define CFG_ATA_ALT_OFFSET      (0x005C)
 364
 365 /* Interval between registers                                                */
 366 #define CFG_ATA_STRIDE          4
 367
 368 /*-----------------------------------------------------------------------
 369  * CPLD stuff
 370  */
 371 #define CFG_FPGA_XC95XL         1       /* using Xilinx XC95XL CPLD      */
 372 #define CFG_FPGA_MAX_SIZE       32*1024 /* 32kByte is enough for CPLD    */
 373
 374 /* CPLD program pin configuration */
 375 #define CFG_FPGA_PRG            0x20000000      /* JTAG TMS pin (ppc output)           */
 376 #define CFG_FPGA_CLK            0x10000000      /* JTAG TCK pin (ppc output)           */
 377 #define CFG_FPGA_DATA           0x20000000      /* JTAG TDO->TDI data pin (ppc output) */
 378 #define CFG_FPGA_DONE           0x10000000      /* JTAG TDI->TDO pin (ppc input)       */
 379
 380 #define JTAG_GPIO_ADDR_TMS      (CFG_MBAR + 0xB10)      /* JTAG TMS pin (GPS data out value reg.)      */
 381 #define JTAG_GPIO_ADDR_TCK      (CFG_MBAR + 0xC0C)      /* JTAG TCK pin (GPW data out value reg.)      */
 382 #define JTAG_GPIO_ADDR_TDI      (CFG_MBAR + 0xC0C)      /* JTAG TDO->TDI pin (GPW data out value reg.) */
 383 #define JTAG_GPIO_ADDR_TDO      (CFG_MBAR + 0xB14)      /* JTAG TDI->TDO pin (GPS data in value reg.)  */
 384
 385 #define JTAG_GPIO_ADDR_CFG      (CFG_MBAR + 0xB00)
 386 #define JTAG_GPIO_CFG_SET       0x00000000
 387 #define JTAG_GPIO_CFG_RESET     0x00F00000
 388
 389 #define JTAG_GPIO_ADDR_EN_TMS   (CFG_MBAR + 0xB04)
 390 #define JTAG_GPIO_TMS_EN_SET    0x20000000      /* Enable for GPIO */
 391 #define JTAG_GPIO_TMS_EN_RESET  0x00000000
 392 #define JTAG_GPIO_ADDR_DDR_TMS  (CFG_MBAR + 0xB0C)
 393 #define JTAG_GPIO_TMS_DDR_SET   0x20000000      /* Set as output   */
 394 #define JTAG_GPIO_TMS_DDR_RESET 0x00000000
 395
 396 #define JTAG_GPIO_ADDR_EN_TCK   (CFG_MBAR + 0xC00)
 397 #define JTAG_GPIO_TCK_EN_SET    0x20000000      /* Enable for GPIO */
 398 #define JTAG_GPIO_TCK_EN_RESET  0x00000000
 399 #define JTAG_GPIO_ADDR_DDR_TCK  (CFG_MBAR + 0xC08)
 400 #define JTAG_GPIO_TCK_DDR_SET   0x20000000      /* Set as output   */
 401 #define JTAG_GPIO_TCK_DDR_RESET 0x00000000
 402
 403 #define JTAG_GPIO_ADDR_EN_TDI   (CFG_MBAR + 0xC00)
 404 #define JTAG_GPIO_TDI_EN_SET    0x10000000      /* Enable as GPIO  */
 405 #define JTAG_GPIO_TDI_EN_RESET  0x00000000
 406 #define JTAG_GPIO_ADDR_DDR_TDI  (CFG_MBAR + 0xC08)
 407 #define JTAG_GPIO_TDI_DDR_SET   0x10000000      /* Set as output   */
 408 #define JTAG_GPIO_TDI_DDR_RESET 0x00000000
 409
 410 #define JTAG_GPIO_ADDR_EN_TDO   (CFG_MBAR + 0xB04)
 411 #define JTAG_GPIO_TDO_EN_SET    0x10000000      /* Enable as GPIO  */
 412 #define JTAG_GPIO_TDO_EN_RESET  0x00000000
 413 #define JTAG_GPIO_ADDR_DDR_TDO  (CFG_MBAR + 0xB0C)
 414 #define JTAG_GPIO_TDO_DDR_SET   0x00000000
 415 #define JTAG_GPIO_TDO_DDR_RESET 0x10000000      /* Set as input    */
 416
 417 #endif                          /* __CONFIG_H */