include/configs/cyrus.h

   1 /*
   2  * Based on corenet_ds.h
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
  11 #error Must call Cyrus CONFIG with a specific CPU enabled.
  12 #endif
  13
  14 #define CONFIG_SDCARD
  15 #define CONFIG_FSL_SATA_V2
  16 #define CONFIG_PCIE3
  17 #define CONFIG_PCIE4
  18 #ifdef CONFIG_ARCH_P5020
  19 #define CONFIG_SYS_FSL_RAID_ENGINE
  20 #define CONFIG_SYS_DPAA_RMAN
  21 #endif
  22 #define CONFIG_SYS_DPAA_PME
  23
  24 /*
  25  * Corenet DS style board configuration file
  26  */
  27 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  28 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  29 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
  30 #if defined(CONFIG_ARCH_P5020)
  31 #define CONFIG_SYS_CLK_FREQ 133000000
  32 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
  33 #elif defined(CONFIG_ARCH_P5040)
  34 #define CONFIG_SYS_CLK_FREQ 100000000
  35 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
  36 #endif
  37
  38 /* High Level Configuration Options */
  39 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  40 #define CONFIG_MP                       /* support multiple processors */
  41
  42 #define CONFIG_SYS_MMC_MAX_DEVICE     1
  43
  44 #ifndef CONFIG_SYS_TEXT_BASE
  45 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  46 #endif
  47
  48 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  49 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  50 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  51 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  52 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  53 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  54
  55 #define CONFIG_ENV_OVERWRITE
  56
  57 #if defined(CONFIG_SDCARD)
  58 #define CONFIG_SYS_EXTRA_ENV_RELOC
  59 #define CONFIG_FSL_FIXED_MMC_LOCATION
  60 #define CONFIG_SYS_MMC_ENV_DEV          0
  61 #define CONFIG_ENV_SIZE                 0x2000
  62 #define CONFIG_ENV_OFFSET               (512 * 1658)
  63 #endif
  64
  65 /*
  66  * These can be toggled for performance analysis, otherwise use default.
  67  */
  68 #define CONFIG_SYS_CACHE_STASHING
  69 #define CONFIG_BACKSIDE_L2_CACHE
  70 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  71 #define CONFIG_BTB                      /* toggle branch predition */
  72 #define CONFIG_DDR_ECC
  73 #ifdef CONFIG_DDR_ECC
  74 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  75 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  76 #endif
  77
  78 #define CONFIG_ENABLE_36BIT_PHYS
  79
  80 #ifdef CONFIG_PHYS_64BIT
  81 #define CONFIG_ADDR_MAP
  82 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  83 #endif
  84
  85 /* test POST memory test */
  86 #undef CONFIG_POST
  87 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  88 #define CONFIG_SYS_MEMTEST_END          0x00400000
  89 #define CONFIG_SYS_ALT_MEMTEST
  90
  91 /*
  92  *  Config the L3 Cache as L3 SRAM
  93  */
  94 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  95 #ifdef CONFIG_PHYS_64BIT
  96 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  97 #else
  98 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  99 #endif
 100 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 101 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 102
 103 #ifdef CONFIG_PHYS_64BIT
 104 #define CONFIG_SYS_DCSRBAR              0xf0000000
 105 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 106 #endif
 107
 108 /*
 109  * DDR Setup
 110  */
 111 #define CONFIG_VERY_BIG_RAM
 112 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 113 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 114
 115 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 116 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 117
 118 #define CONFIG_DDR_SPD
 119
 120 #define CONFIG_SYS_SPD_BUS_NUM  1
 121 #define SPD_EEPROM_ADDRESS1     0x51
 122 #define SPD_EEPROM_ADDRESS2     0x52
 123 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 124
 125 /*
 126  * Local Bus Definitions
 127  */
 128
 129 #define CONFIG_SYS_LBC0_BASE            0xe0000000 /* Start of LBC Registers */
 130 #ifdef CONFIG_PHYS_64BIT
 131 #define CONFIG_SYS_LBC0_BASE_PHYS       0xfe0000000ull
 132 #else
 133 #define CONFIG_SYS_LBC0_BASE_PHYS       CONFIG_SYS_LBC0_BASE
 134 #endif
 135
 136 #define CONFIG_SYS_LBC1_BASE            0xe1000000 /* Start of LBC Registers */
 137 #ifdef CONFIG_PHYS_64BIT
 138 #define CONFIG_SYS_LBC1_BASE_PHYS       0xfe1000000ull
 139 #else
 140 #define CONFIG_SYS_LBC1_BASE_PHYS       CONFIG_SYS_LBC1_BASE
 141 #endif
 142
 143 /* Set the local bus clock 1/16 of platform clock */
 144 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_16 | LCRR_EADC_1)
 145
 146 #define CONFIG_SYS_BR0_PRELIM \
 147 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
 148 #define CONFIG_SYS_BR1_PRELIM \
 149 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
 150
 151 #define CONFIG_SYS_OR0_PRELIM   0xfff00010
 152 #define CONFIG_SYS_OR1_PRELIM   0xfff00010
 153
 154 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 155
 156 #if defined(CONFIG_RAMBOOT_PBL)
 157 #define CONFIG_SYS_RAMBOOT
 158 #endif
 159
 160 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 161 #define CONFIG_MISC_INIT_R
 162
 163 #define CONFIG_HWCONFIG
 164
 165 /* define to use L1 as initial stack */
 166 #define CONFIG_L1_INIT_RAM
 167 #define CONFIG_SYS_INIT_RAM_LOCK
 168 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 169 #ifdef CONFIG_PHYS_64BIT
 170 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 171 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 172 /* The assembler doesn't like typecast */
 173 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 174         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 175           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 176 #else
 177 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 178 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 179 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 180 #endif
 181 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 182
 183 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 184 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 185
 186 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 187 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 188
 189 /* Serial Port - controlled on board with jumper J8
 190  * open - index 2
 191  * shorted - index 1
 192  */
 193 #define CONFIG_CONS_INDEX       1
 194 #define CONFIG_SYS_NS16550_SERIAL
 195 #define CONFIG_SYS_NS16550_REG_SIZE     1
 196 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 197
 198 #define CONFIG_SYS_BAUDRATE_TABLE       \
 199 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 200
 201 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 202 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 203 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 204 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 205
 206 /* I2C */
 207 #define CONFIG_SYS_I2C
 208 #define CONFIG_SYS_I2C_FSL
 209 #define CONFIG_I2C_MULTI_BUS
 210 #define CONFIG_I2C_CMD_TREE
 211 #define CONFIG_SYS_FSL_I2C_SPEED                400000  /* I2C speed and slave address */
 212 #define CONFIG_SYS_FSL_I2C_SLAVE                0x7F
 213 #define CONFIG_SYS_FSL_I2C_OFFSET               0x118000
 214 #define CONFIG_SYS_FSL_I2C2_SPEED               400000  /* I2C speed and slave address */
 215 #define CONFIG_SYS_FSL_I2C2_SLAVE               0x7F
 216 #define CONFIG_SYS_FSL_I2C2_OFFSET              0x118100
 217 #define CONFIG_SYS_FSL_I2C3_SPEED               400000  /* I2C speed and slave address */
 218 #define CONFIG_SYS_FSL_I2C3_SLAVE               0x7F
 219 #define CONFIG_SYS_FSL_I2C3_OFFSET              0x119000
 220 #define CONFIG_SYS_FSL_I2C4_SPEED               400000  /* I2C speed and slave address */
 221 #define CONFIG_SYS_FSL_I2C4_SLAVE               0x7F
 222 #define CONFIG_SYS_FSL_I2C4_OFFSET              0x119100
 223
 224 #define CONFIG_ID_EEPROM
 225 #define CONFIG_SYS_I2C_EEPROM_NXID
 226 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 227 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 228 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 229
 230 #define CONFIG_SYS_I2C_GENERIC_MAC
 231 #define CONFIG_SYS_I2C_MAC1_BUS 3
 232 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
 233 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
 234 #define CONFIG_SYS_I2C_MAC2_BUS 0
 235 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
 236 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
 237
 238 #define CONFIG_RTC_MCP79411             1
 239 #define CONFIG_SYS_RTC_BUS_NUM          3
 240 #define CONFIG_SYS_I2C_RTC_ADDR         0x6f
 241
 242 /*
 243  * eSPI - Enhanced SPI
 244  */
 245
 246 /*
 247  * General PCI
 248  * Memory space is mapped 1-1, but I/O space must start from 0.
 249  */
 250
 251 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 252 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 253 #ifdef CONFIG_PHYS_64BIT
 254 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 255 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 256 #else
 257 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 258 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 259 #endif
 260 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 261 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 262 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 263 #ifdef CONFIG_PHYS_64BIT
 264 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 265 #else
 266 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 267 #endif
 268 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 269
 270 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 271 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 272 #ifdef CONFIG_PHYS_64BIT
 273 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 274 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 275 #else
 276 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 277 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 278 #endif
 279 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 280 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 281 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 282 #ifdef CONFIG_PHYS_64BIT
 283 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 284 #else
 285 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 286 #endif
 287 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 288
 289 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 290 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 291 #ifdef CONFIG_PHYS_64BIT
 292 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 293 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 294 #else
 295 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 296 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 297 #endif
 298 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 299 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 300 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 301 #ifdef CONFIG_PHYS_64BIT
 302 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 303 #else
 304 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 305 #endif
 306 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 307
 308 /* controller 4, Base address 203000 */
 309 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 310 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 311 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 312 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 313 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 314 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 315
 316 /* Qman/Bman */
 317 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 318 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 319 #ifdef CONFIG_PHYS_64BIT
 320 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 321 #else
 322 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 323 #endif
 324 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 325 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 326 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 327 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 328 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 329 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 330                                          CONFIG_SYS_BMAN_CENA_SIZE)
 331 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 332 #define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
 333 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 334 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 335 #ifdef CONFIG_PHYS_64BIT
 336 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 337 #else
 338 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 339 #endif
 340 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 341 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 342 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 343 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 344 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 345 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 346                                           CONFIG_SYS_QMAN_CENA_SIZE)
 347 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 348 #define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08
 349
 350 #define CONFIG_SYS_DPAA_FMAN
 351 /* Default address of microcode for the Linux Fman driver */
 352 /*
 353  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 354  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 355  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 356  */
 357 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 358 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 359
 360 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 361 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 362
 363 #ifdef CONFIG_SYS_DPAA_FMAN
 364 #define CONFIG_FMAN_ENET
 365 #endif
 366
 367 #ifdef CONFIG_PCI
 368 #define CONFIG_PCI_INDIRECT_BRIDGE
 369
 370 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 371 #endif  /* CONFIG_PCI */
 372
 373 /* SATA */
 374 #ifdef CONFIG_FSL_SATA_V2
 375 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 376 #define CONFIG_SATA1
 377 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 378 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 379 #define CONFIG_SATA2
 380 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 381 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 382
 383 #define CONFIG_LBA48
 384 #endif
 385
 386 #ifdef CONFIG_FMAN_ENET
 387 #define CONFIG_SYS_TBIPA_VALUE  8
 388 #define CONFIG_MII              /* MII PHY management */
 389 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 390 #endif
 391
 392 /*
 393  * Environment
 394  */
 395 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 396 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 397
 398 /*
 399  * USB
 400  */
 401 #define CONFIG_HAS_FSL_DR_USB
 402 #define CONFIG_HAS_FSL_MPH_USB
 403
 404 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 405 #define CONFIG_USB_EHCI_FSL
 406 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 407 #define CONFIG_EHCI_IS_TDI
 408  /* _VIA_CONTROL_EP  */
 409 #endif
 410
 411 #ifdef CONFIG_MMC
 412 #define CONFIG_FSL_ESDHC
 413 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 414 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 415 #endif
 416
 417 /*
 418  * Miscellaneous configurable options
 419  */
 420 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 421 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 422 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 423 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 424
 425 /*
 426  * For booting Linux, the board info and command line data
 427  * have to be in the first 64 MB of memory, since this is
 428  * the maximum mapped by the Linux kernel during initialization.
 429  */
 430 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 431 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 432
 433 #ifdef CONFIG_CMD_KGDB
 434 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 435 #endif
 436
 437 /*
 438  * Environment Configuration
 439  */
 440 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 441 #define CONFIG_BOOTFILE         "uImage"
 442 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 443
 444 /* default location for tftp and bootm */
 445 #define CONFIG_LOADADDR         1000000
 446
 447 #define __USB_PHY_TYPE  utmi
 448
 449 #define CONFIG_EXTRA_ENV_SETTINGS \
 450 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 451 "bank_intlv=cs0_cs1;"                                   \
 452 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 453 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 454 "netdev=eth0\0"                                         \
 455 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 456 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 457 "consoledev=ttyS0\0"                                    \
 458 "ramdiskaddr=2000000\0"                                 \
 459 "fdtaddr=1e00000\0"                                     \
 460 "bdev=sda3\0"
 461
 462 #define CONFIG_HDBOOT                                   \
 463 "setenv bootargs root=/dev/$bdev rw "           \
 464 "console=$consoledev,$baudrate $othbootargs;"   \
 465 "tftp $loadaddr $bootfile;"                     \
 466 "tftp $fdtaddr $fdtfile;"                       \
 467 "bootm $loadaddr - $fdtaddr"
 468
 469 #define CONFIG_NFSBOOTCOMMAND                   \
 470 "setenv bootargs root=/dev/nfs rw "     \
 471 "nfsroot=$serverip:$rootpath "          \
 472 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 473 "console=$consoledev,$baudrate $othbootargs;"   \
 474 "tftp $loadaddr $bootfile;"             \
 475 "tftp $fdtaddr $fdtfile;"               \
 476 "bootm $loadaddr - $fdtaddr"
 477
 478 #define CONFIG_RAMBOOTCOMMAND                           \
 479 "setenv bootargs root=/dev/ram rw "             \
 480 "console=$consoledev,$baudrate $othbootargs;"   \
 481 "tftp $ramdiskaddr $ramdiskfile;"               \
 482 "tftp $loadaddr $bootfile;"                     \
 483 "tftp $fdtaddr $fdtfile;"                       \
 484 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 485
 486 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 487
 488 #include <asm/fsl_secure_boot.h>
 489
 490 #ifdef CONFIG_SECURE_BOOT
 491 #endif
 492
 493 #endif  /* __CONFIG_H */