include/configs/cyrus.h

   1 /*
   2  * Based on corenet_ds.h
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_CYRUS
  11
  12 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040)
  13 #error Must call Cyrus CONFIG with a specific CPU enabled.
  14 #endif
  15
  16 #define CONFIG_SDCARD
  17 #define CONFIG_FSL_SATA_V2
  18 #define CONFIG_PCIE3
  19 #define CONFIG_PCIE4
  20 #ifdef CONFIG_ARCH_P5020
  21 #define CONFIG_SYS_FSL_RAID_ENGINE
  22 #define CONFIG_SYS_DPAA_RMAN
  23 #endif
  24 #define CONFIG_SYS_DPAA_PME
  25
  26 /*
  27  * Corenet DS style board configuration file
  28  */
  29 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  30 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  31 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
  32 #if defined(CONFIG_ARCH_P5020)
  33 #define CONFIG_SYS_CLK_FREQ 133000000
  34 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
  35 #elif defined(CONFIG_ARCH_P5040)
  36 #define CONFIG_SYS_CLK_FREQ 100000000
  37 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
  38 #endif
  39
  40 /* High Level Configuration Options */
  41 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  42 #define CONFIG_MP                       /* support multiple processors */
  43
  44 #define CONFIG_SYS_MMC_MAX_DEVICE     1
  45
  46 #ifndef CONFIG_SYS_TEXT_BASE
  47 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  48 #endif
  49
  50 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  51 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  52 #define CONFIG_FSL_ELBC                 /* Has Enhanced localbus controller */
  53 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  54 #define CONFIG_PCIE2                    /* PCIE controller 2 */
  55 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  56 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  57
  58 #define CONFIG_ENV_OVERWRITE
  59
  60 #define CONFIG_SYS_NO_FLASH
  61
  62 #if defined(CONFIG_SDCARD)
  63 #define CONFIG_SYS_EXTRA_ENV_RELOC
  64 #define CONFIG_ENV_IS_IN_MMC
  65 #define CONFIG_FSL_FIXED_MMC_LOCATION
  66 #define CONFIG_SYS_MMC_ENV_DEV          0
  67 #define CONFIG_ENV_SIZE                 0x2000
  68 #define CONFIG_ENV_OFFSET               (512 * 1658)
  69 #endif
  70
  71 /*
  72  * These can be toggled for performance analysis, otherwise use default.
  73  */
  74 #define CONFIG_SYS_CACHE_STASHING
  75 #define CONFIG_BACKSIDE_L2_CACHE
  76 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  77 #define CONFIG_BTB                      /* toggle branch predition */
  78 #define CONFIG_DDR_ECC
  79 #ifdef CONFIG_DDR_ECC
  80 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  81 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  82 #endif
  83
  84 #define CONFIG_ENABLE_36BIT_PHYS
  85
  86 #ifdef CONFIG_PHYS_64BIT
  87 #define CONFIG_ADDR_MAP
  88 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  89 #endif
  90
  91 /* test POST memory test */
  92 #undef CONFIG_POST
  93 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
  94 #define CONFIG_SYS_MEMTEST_END          0x00400000
  95 #define CONFIG_SYS_ALT_MEMTEST
  96 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
  97
  98 /*
  99  *  Config the L3 Cache as L3 SRAM
 100  */
 101 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
 102 #ifdef CONFIG_PHYS_64BIT
 103 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
 104 #else
 105 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
 106 #endif
 107 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
 108 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
 109
 110 #ifdef CONFIG_PHYS_64BIT
 111 #define CONFIG_SYS_DCSRBAR              0xf0000000
 112 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 113 #endif
 114
 115 /*
 116  * DDR Setup
 117  */
 118 #define CONFIG_VERY_BIG_RAM
 119 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 120 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 121
 122 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 123 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 124
 125 #define CONFIG_DDR_SPD
 126 #define CONFIG_SYS_FSL_DDR3
 127
 128 #define CONFIG_SYS_SPD_BUS_NUM  1
 129 #define SPD_EEPROM_ADDRESS1     0x51
 130 #define SPD_EEPROM_ADDRESS2     0x52
 131 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
 132
 133 /*
 134  * Local Bus Definitions
 135  */
 136
 137 #define CONFIG_SYS_LBC0_BASE            0xe0000000 /* Start of LBC Registers */
 138 #ifdef CONFIG_PHYS_64BIT
 139 #define CONFIG_SYS_LBC0_BASE_PHYS       0xfe0000000ull
 140 #else
 141 #define CONFIG_SYS_LBC0_BASE_PHYS       CONFIG_SYS_LBC0_BASE
 142 #endif
 143
 144 #define CONFIG_SYS_LBC1_BASE            0xe1000000 /* Start of LBC Registers */
 145 #ifdef CONFIG_PHYS_64BIT
 146 #define CONFIG_SYS_LBC1_BASE_PHYS       0xfe1000000ull
 147 #else
 148 #define CONFIG_SYS_LBC1_BASE_PHYS       CONFIG_SYS_LBC1_BASE
 149 #endif
 150
 151 /* Set the local bus clock 1/16 of platform clock */
 152 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_16 | LCRR_EADC_1)
 153
 154 #define CONFIG_SYS_BR0_PRELIM \
 155 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
 156 #define CONFIG_SYS_BR1_PRELIM \
 157 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
 158
 159 #define CONFIG_SYS_OR0_PRELIM   0xfff00010
 160 #define CONFIG_SYS_OR1_PRELIM   0xfff00010
 161
 162 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE    /* start of monitor */
 163
 164 #if defined(CONFIG_RAMBOOT_PBL)
 165 #define CONFIG_SYS_RAMBOOT
 166 #endif
 167
 168 #define CONFIG_BOARD_EARLY_INIT_F
 169 #define CONFIG_BOARD_EARLY_INIT_R       /* call board_early_init_r function */
 170 #define CONFIG_MISC_INIT_R
 171
 172 #define CONFIG_HWCONFIG
 173
 174 /* define to use L1 as initial stack */
 175 #define CONFIG_L1_INIT_RAM
 176 #define CONFIG_SYS_INIT_RAM_LOCK
 177 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 178 #ifdef CONFIG_PHYS_64BIT
 179 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 180 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 181 /* The assembler doesn't like typecast */
 182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 183         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 184           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 185 #else
 186 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
 187 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 188 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 189 #endif
 190 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000      /* Size of used area in RAM */
 191
 192 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 193 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 194
 195 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 196 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc */
 197
 198 /* Serial Port - controlled on board with jumper J8
 199  * open - index 2
 200  * shorted - index 1
 201  */
 202 #define CONFIG_CONS_INDEX       1
 203 #define CONFIG_SYS_NS16550_SERIAL
 204 #define CONFIG_SYS_NS16550_REG_SIZE     1
 205 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 206
 207 #define CONFIG_SYS_BAUDRATE_TABLE       \
 208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 209
 210 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 211 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 212 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 213 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 214
 215 /* I2C */
 216 #define CONFIG_SYS_I2C
 217 #define CONFIG_SYS_I2C_FSL
 218 #define CONFIG_I2C_MULTI_BUS
 219 #define CONFIG_I2C_CMD_TREE
 220 #define CONFIG_SYS_FSL_I2C_SPEED                400000  /* I2C speed and slave address */
 221 #define CONFIG_SYS_FSL_I2C_SLAVE                0x7F
 222 #define CONFIG_SYS_FSL_I2C_OFFSET               0x118000
 223 #define CONFIG_SYS_FSL_I2C2_SPEED               400000  /* I2C speed and slave address */
 224 #define CONFIG_SYS_FSL_I2C2_SLAVE               0x7F
 225 #define CONFIG_SYS_FSL_I2C2_OFFSET              0x118100
 226 #define CONFIG_SYS_FSL_I2C3_SPEED               400000  /* I2C speed and slave address */
 227 #define CONFIG_SYS_FSL_I2C3_SLAVE               0x7F
 228 #define CONFIG_SYS_FSL_I2C3_OFFSET              0x119000
 229 #define CONFIG_SYS_FSL_I2C4_SPEED               400000  /* I2C speed and slave address */
 230 #define CONFIG_SYS_FSL_I2C4_SLAVE               0x7F
 231 #define CONFIG_SYS_FSL_I2C4_OFFSET              0x119100
 232
 233 #define CONFIG_ID_EEPROM
 234 #define CONFIG_SYS_I2C_EEPROM_NXID
 235 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 236 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 237 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 238
 239 #define CONFIG_SYS_I2C_GENERIC_MAC
 240 #define CONFIG_SYS_I2C_MAC1_BUS 3
 241 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
 242 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
 243 #define CONFIG_SYS_I2C_MAC2_BUS 0
 244 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
 245 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
 246
 247 #define CONFIG_CMD_DATE                 1
 248 #define CONFIG_RTC_MCP79411             1
 249 #define CONFIG_SYS_RTC_BUS_NUM          3
 250 #define CONFIG_SYS_I2C_RTC_ADDR         0x6f
 251
 252 /*
 253  * eSPI - Enhanced SPI
 254  */
 255
 256 /*
 257  * General PCI
 258  * Memory space is mapped 1-1, but I/O space must start from 0.
 259  */
 260
 261 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 262 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 263 #ifdef CONFIG_PHYS_64BIT
 264 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 265 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 266 #else
 267 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 268 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 269 #endif
 270 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 271 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 272 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 273 #ifdef CONFIG_PHYS_64BIT
 274 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 275 #else
 276 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 277 #endif
 278 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 279
 280 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 281 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 282 #ifdef CONFIG_PHYS_64BIT
 283 #define CONFIG_SYS_PCIE2_MEM_BUS        0xe0000000
 284 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 285 #else
 286 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 287 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 288 #endif
 289 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 290 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 291 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 292 #ifdef CONFIG_PHYS_64BIT
 293 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 294 #else
 295 #define CONFIG_SYS_PCIE2_IO_PHYS        0xf8010000
 296 #endif
 297 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 298
 299 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 300 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 301 #ifdef CONFIG_PHYS_64BIT
 302 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 303 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 304 #else
 305 #define CONFIG_SYS_PCIE3_MEM_BUS        0xc0000000
 306 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc0000000
 307 #endif
 308 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 309 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 310 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 311 #ifdef CONFIG_PHYS_64BIT
 312 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 313 #else
 314 #define CONFIG_SYS_PCIE3_IO_PHYS        0xf8020000
 315 #endif
 316 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 317
 318 /* controller 4, Base address 203000 */
 319 #define CONFIG_SYS_PCIE4_MEM_BUS        0xe0000000
 320 #define CONFIG_SYS_PCIE4_MEM_PHYS       0xc60000000ull
 321 #define CONFIG_SYS_PCIE4_MEM_SIZE       0x20000000      /* 512M */
 322 #define CONFIG_SYS_PCIE4_IO_BUS         0x00000000
 323 #define CONFIG_SYS_PCIE4_IO_PHYS        0xff8030000ull
 324 #define CONFIG_SYS_PCIE4_IO_SIZE        0x00010000      /* 64k */
 325
 326 /* Qman/Bman */
 327 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 328 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 329 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 330 #ifdef CONFIG_PHYS_64BIT
 331 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 332 #else
 333 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 334 #endif
 335 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 336 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 337 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 338 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 339 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 340 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 341                                          CONFIG_SYS_BMAN_CENA_SIZE)
 342 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 343 #define CONFIG_SYS_BMAN_SWP_ISDR_REG   0xE08
 344 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 345 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 346 #ifdef CONFIG_PHYS_64BIT
 347 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 348 #else
 349 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 350 #endif
 351 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 352 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 353 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 354 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 355 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 356 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 357                                           CONFIG_SYS_QMAN_CENA_SIZE)
 358 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 359 #define CONFIG_SYS_QMAN_SWP_ISDR_REG   0xE08
 360
 361 #define CONFIG_SYS_DPAA_FMAN
 362 /* Default address of microcode for the Linux Fman driver */
 363 /*
 364  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 365  * about 825KB (1650 blocks), Env is stored after the image, and the env size is
 366  * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
 367  */
 368 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 369 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
 370
 371 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 372 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 373
 374 #ifdef CONFIG_SYS_DPAA_FMAN
 375 #define CONFIG_FMAN_ENET
 376 #define CONFIG_PHY_MICREL
 377 #define CONFIG_PHY_MICREL_KSZ9021
 378 #endif
 379
 380 #ifdef CONFIG_PCI
 381 #define CONFIG_PCI_INDIRECT_BRIDGE
 382 #define CONFIG_NET_MULTI
 383
 384 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 385 #define CONFIG_DOS_PARTITION
 386 #endif  /* CONFIG_PCI */
 387
 388 /* SATA */
 389 #ifdef CONFIG_FSL_SATA_V2
 390 #define CONFIG_LIBATA
 391 #define CONFIG_FSL_SATA
 392
 393 #define CONFIG_SYS_SATA_MAX_DEVICE      2
 394 #define CONFIG_SATA1
 395 #define CONFIG_SYS_SATA1                CONFIG_SYS_MPC85xx_SATA1_ADDR
 396 #define CONFIG_SYS_SATA1_FLAGS          FLAGS_DMA
 397 #define CONFIG_SATA2
 398 #define CONFIG_SYS_SATA2                CONFIG_SYS_MPC85xx_SATA2_ADDR
 399 #define CONFIG_SYS_SATA2_FLAGS          FLAGS_DMA
 400
 401 #define CONFIG_LBA48
 402 #define CONFIG_CMD_SATA
 403 #define CONFIG_DOS_PARTITION
 404 #endif
 405
 406 #ifdef CONFIG_FMAN_ENET
 407 #define CONFIG_SYS_TBIPA_VALUE  8
 408 #define CONFIG_MII              /* MII PHY management */
 409 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
 410 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 411 #endif
 412
 413 /*
 414  * Environment
 415  */
 416 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 417 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 418
 419 /*
 420  * Command line configuration.
 421  */
 422 #define CONFIG_CMD_ERRATA
 423 #define CONFIG_CMD_IRQ
 424 #define CONFIG_CMD_REGINFO
 425
 426 #ifdef CONFIG_PCI
 427 #define CONFIG_CMD_PCI
 428 #endif
 429
 430 /*
 431  * USB
 432  */
 433 #define CONFIG_HAS_FSL_DR_USB
 434 #define CONFIG_HAS_FSL_MPH_USB
 435
 436 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
 437 #define CONFIG_USB_EHCI
 438 #define CONFIG_USB_EHCI_FSL
 439 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 440 #define CONFIG_EHCI_IS_TDI
 441 #define CONFIG_SYS_USB_EVENT_POLL
 442  /* _VIA_CONTROL_EP  */
 443 #endif
 444
 445 #ifdef CONFIG_MMC
 446 #define CONFIG_FSL_ESDHC
 447 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 448 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
 449 #define CONFIG_GENERIC_MMC
 450 #define CONFIG_DOS_PARTITION
 451 #endif
 452
 453 /*
 454  * Miscellaneous configurable options
 455  */
 456 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 457 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 458 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 459 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 460 #ifdef CONFIG_CMD_KGDB
 461 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 462 #else
 463 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 464 #endif
 465 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 466 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 467 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 468
 469 /*
 470  * For booting Linux, the board info and command line data
 471  * have to be in the first 64 MB of memory, since this is
 472  * the maximum mapped by the Linux kernel during initialization.
 473  */
 474 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory map for Linux*/
 475 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 476
 477 #ifdef CONFIG_CMD_KGDB
 478 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 479 #endif
 480
 481 /*
 482  * Environment Configuration
 483  */
 484 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 485 #define CONFIG_BOOTFILE         "uImage"
 486 #define CONFIG_UBOOTPATH        u-boot.bin      /* U-Boot image on TFTP server */
 487
 488 /* default location for tftp and bootm */
 489 #define CONFIG_LOADADDR         1000000
 490
 491
 492 #define CONFIG_BAUDRATE 115200
 493
 494 #define __USB_PHY_TYPE  utmi
 495
 496 #define CONFIG_EXTRA_ENV_SETTINGS \
 497 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 498 "bank_intlv=cs0_cs1;"                                   \
 499 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
 500 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 501 "netdev=eth0\0"                                         \
 502 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 503 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 504 "consoledev=ttyS0\0"                                    \
 505 "ramdiskaddr=2000000\0"                                 \
 506 "fdtaddr=1e00000\0"                                     \
 507 "bdev=sda3\0"
 508
 509 #define CONFIG_HDBOOT                                   \
 510 "setenv bootargs root=/dev/$bdev rw "           \
 511 "console=$consoledev,$baudrate $othbootargs;"   \
 512 "tftp $loadaddr $bootfile;"                     \
 513 "tftp $fdtaddr $fdtfile;"                       \
 514 "bootm $loadaddr - $fdtaddr"
 515
 516 #define CONFIG_NFSBOOTCOMMAND                   \
 517 "setenv bootargs root=/dev/nfs rw "     \
 518 "nfsroot=$serverip:$rootpath "          \
 519 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 520 "console=$consoledev,$baudrate $othbootargs;"   \
 521 "tftp $loadaddr $bootfile;"             \
 522 "tftp $fdtaddr $fdtfile;"               \
 523 "bootm $loadaddr - $fdtaddr"
 524
 525 #define CONFIG_RAMBOOTCOMMAND                           \
 526 "setenv bootargs root=/dev/ram rw "             \
 527 "console=$consoledev,$baudrate $othbootargs;"   \
 528 "tftp $ramdiskaddr $ramdiskfile;"               \
 529 "tftp $loadaddr $bootfile;"                     \
 530 "tftp $fdtaddr $fdtfile;"                       \
 531 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 532
 533 #define CONFIG_BOOTCOMMAND              CONFIG_HDBOOT
 534
 535 #include <asm/fsl_secure_boot.h>
 536
 537 #ifdef CONFIG_SECURE_BOOT
 538 #endif
 539
 540 #endif  /* __CONFIG_H */