include/configs/db-mv784mp-gp.h

   1 /*
   2  * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _CONFIG_DB_MV7846MP_GP_H
   8 #define _CONFIG_DB_MV7846MP_GP_H
   9
  10 /*
  11  * High Level Configuration Options (easy to change)
  12  */
  13 #define CONFIG_DB_784MP_GP              /* Board target name for DDR training */
  14
  15 #define CONFIG_DISPLAY_BOARDINFO_LATE
  16
  17 /*
  18  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  19  * for DDR ECC byte filling in the SPL before loading the main
  20  * U-Boot into it.
  21  */
  22 #define CONFIG_SYS_TEXT_BASE    0x00800000
  23 #define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  24
  25 /*
  26  * Commands configuration
  27  */
  28 #define CONFIG_CMD_NAND
  29 #define CONFIG_CMD_PCI
  30
  31 /* I2C */
  32 #define CONFIG_SYS_I2C
  33 #define CONFIG_SYS_I2C_MVTWSI
  34 #define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  35 #define CONFIG_SYS_I2C_SLAVE            0x0
  36 #define CONFIG_SYS_I2C_SPEED            100000
  37
  38 /* USB/EHCI configuration */
  39 #define CONFIG_EHCI_IS_TDI
  40 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  41
  42 /* SPI NOR flash default params, used by sf commands */
  43 #define CONFIG_SF_DEFAULT_SPEED         1000000
  44 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_3
  45
  46 /* Environment in SPI NOR flash */
  47 #define CONFIG_ENV_OFFSET               (1 << 20) /* 1MiB in */
  48 #define CONFIG_ENV_SIZE                 (64 << 10) /* 64KiB */
  49 #define CONFIG_ENV_SECT_SIZE            (64 << 10) /* 64KiB sectors */
  50
  51 #define CONFIG_PHY_MARVELL              /* there is a marvell phy */
  52 #define PHY_ANEG_TIMEOUT        8000    /* PHY needs a longer aneg time */
  53
  54 #define CONFIG_SYS_ALT_MEMTEST
  55
  56 /* SATA support */
  57 #define CONFIG_SYS_SATA_MAX_DEVICE      2
  58 #define CONFIG_SATA_MV
  59 #define CONFIG_LIBATA
  60 #define CONFIG_LBA48
  61
  62 /* Additional FS support/configuration */
  63 #define CONFIG_SUPPORT_VFAT
  64
  65 /* PCIe support */
  66 #ifndef CONFIG_SPL_BUILD
  67 #define CONFIG_PCI_MVEBU
  68 #define CONFIG_PCI_SCAN_SHOW
  69 #endif
  70
  71 /* NAND */
  72 #define CONFIG_SYS_NAND_USE_FLASH_BBT
  73 #define CONFIG_SYS_NAND_ONFI_DETECTION
  74
  75 /*
  76  * mv-common.h should be defined after CMD configs since it used them
  77  * to enable certain macros
  78  */
  79 #include "mv-common.h"
  80
  81 /*
  82  * Memory layout while starting into the bin_hdr via the
  83  * BootROM:
  84  *
  85  * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
  86  * 0x4000.4030                  bin_hdr start address
  87  * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
  88  * 0x4007.fffc                  BootROM stack top
  89  *
  90  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  91  * L2 cache thus cannot be used.
  92  */
  93
  94 /* SPL */
  95 /* Defines for SPL */
  96 #define CONFIG_SPL_FRAMEWORK
  97 #define CONFIG_SPL_TEXT_BASE            0x40004030
  98 #define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
  99
 100 #define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
 101 #define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
 102
 103 #ifdef CONFIG_SPL_BUILD
 104 #define CONFIG_SYS_MALLOC_SIMPLE
 105 #endif
 106
 107 #define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
 108 #define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
 109
 110 /* SPL related SPI defines */
 111 #define CONFIG_SPL_SPI_LOAD
 112 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x20000
 113 #define CONFIG_SYS_U_BOOT_OFFS          CONFIG_SYS_SPI_U_BOOT_OFFS
 114
 115 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 116 #define CONFIG_SPD_EEPROM               0x4e
 117 #define CONFIG_BOARD_ECC_SUPPORT        /* this board supports ECC */
 118
 119 #endif /* _CONFIG_DB_MV7846MP_GP_H */