include/configs/devkit8000.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Texas Instruments.
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  * Syed Mohammed Khasim <x0khasim@ti.com>
   6  *
   7  * (C) Copyright 2009
   8  * Frederik Kriewitz <frederik@kriewitz.eu>
   9  *
  10  * Configuration settings for the DevKit8000 board.
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #ifndef __CONFIG_H
  16 #define __CONFIG_H
  17
  18 /* High Level Configuration Options */
  19 #define CONFIG_OMAP3_DEVKIT8000 1       /* working with DevKit8000 */
  20 #define CONFIG_MACH_TYPE        MACH_TYPE_DEVKIT8000
  21
  22 /*
  23  * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  24  * 64 bytes before this address should be set aside for u-boot.img's
  25  * header. That is 0x800FFFC0--0x80100000 should not be used for any
  26  * other needs.
  27  */
  28 #define CONFIG_SYS_TEXT_BASE    0x80100000
  29
  30 #define CONFIG_SPL_BSS_START_ADDR       0x80000500 /* leave space for bootargs*/
  31 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  32
  33 #define CONFIG_SYS_SPL_MALLOC_START     0x80208000
  34 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000        /* 1 MB */
  35
  36 #include <asm/arch/cpu.h>               /* get chip and board defs */
  37 #include <asm/arch/omap3.h>
  38
  39 #define CONFIG_SDRC     /* The chip has SDRC controller */
  40 #define CONFIG_NAND
  41 #define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
  42                                                         /* to access nand at */
  43                                                         /* CS0 */
  44
  45 /*  Physical Memory Map  */
  46 #define CONFIG_NR_DRAM_BANKS            2 /* CS1 may or may not be populated */
  47 #define PHYS_SDRAM_1                    OMAP34XX_SDRC_CS0
  48 #define PHYS_SDRAM_2                    OMAP34XX_SDRC_CS1
  49
  50 #include <configs/ti_armv7_common.h>
  51
  52 /* Display CPU and Board information */
  53 #define CONFIG_DISPLAY_CPUINFO          1
  54 #define CONFIG_DISPLAY_BOARDINFO        1
  55
  56 /* Clock Defines */
  57 #define V_OSCK                          26000000        /* Clock output from T2 */
  58 #define V_SCLK                          (V_OSCK >> 1)
  59
  60 #define CONFIG_MISC_INIT_R
  61
  62 #define CONFIG_REVISION_TAG             1
  63
  64 /* Size of malloc() pool */
  65 #define CONFIG_ENV_SIZE                 (128 << 10)     /* 128 KiB */
  66                                                 /* Sector */
  67 #undef CONFIG_SYS_MALLOC_LEN
  68 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (128 << 10))
  69
  70 /* Hardware drivers */
  71 /* DM9000 */
  72 #define CONFIG_NET_RETRY_COUNT          20
  73 #define CONFIG_DRIVER_DM9000            1
  74 #define CONFIG_DM9000_BASE              0x2c000000
  75 #define DM9000_IO                       CONFIG_DM9000_BASE
  76 #define DM9000_DATA                     (CONFIG_DM9000_BASE + 0x400)
  77 #define CONFIG_DM9000_USE_16BIT         1
  78 #define CONFIG_DM9000_NO_SROM           1
  79 #undef  CONFIG_DM9000_DEBUG
  80
  81 /* NS16550 Configuration */
  82 #define CONFIG_SYS_NS16550
  83 #define CONFIG_SYS_NS16550_SERIAL
  84 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  85 #define CONFIG_SYS_NS16550_CLK          48000000 /* 48MHz (APLL96/2) */
  86
  87 /* select serial console configuration */
  88 #define CONFIG_CONS_INDEX               3
  89 #define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  90 #define CONFIG_SERIAL3                  3
  91 #define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  92                                         115200}
  93
  94 /* SPI */
  95 #undef CONFIG_SPI
  96 #undef CONFIG_OMAP3_SPI
  97
  98 /* I2C */
  99 #undef CONFIG_SYS_I2C_OMAP24XX
 100 #define CONFIG_SYS_I2C_OMAP34XX
 101
 102 /* TWL4030 */
 103 #define CONFIG_TWL4030_POWER            1
 104 #define CONFIG_TWL4030_LED              1
 105
 106 /* Board NAND Info */
 107 #define MTDIDS_DEFAULT                  "nand0=nand"
 108 #define MTDPARTS_DEFAULT                "mtdparts=nand:" \
 109                                                 "512k(x-loader)," \
 110                                                 "1920k(u-boot)," \
 111                                                 "128k(u-boot-env)," \
 112                                                 "4m(kernel)," \
 113                                                 "-(fs)"
 114
 115 #define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 116                                                         /* to access nand */
 117 #define CONFIG_JFFS2_NAND
 118 /* nand device jffs2 lives on */
 119 #define CONFIG_JFFS2_DEV                "nand0"
 120 /* start of jffs2 partition */
 121 #define CONFIG_JFFS2_PART_OFFSET        0x680000
 122 #define CONFIG_JFFS2_PART_SIZE          0xf980000       /* size of jffs2 */
 123                                                         /* partition */
 124
 125 /* commands to include */
 126 #define CONFIG_CMD_DHCP                 /* DHCP support                 */
 127 #define CONFIG_CMD_JFFS2                /* JFFS2 Support                */
 128 #define CONFIG_CMD_NAND_LOCK_UNLOCK     /* nand (un)lock commands       */
 129
 130 #undef CONFIG_CMD_FPGA                  /* FPGA configuration Support   */
 131 #undef CONFIG_CMD_IMI                   /* iminfo                       */
 132 #undef CONFIG_CMD_SPI
 133 #undef CONFIG_CMD_GPIO
 134 #undef CONFIG_CMD_ASKENV
 135 #undef CONFIG_CMD_BOOTZ
 136 #undef CONFIG_SUPPORT_RAW_INITRD
 137 #undef CONFIG_FAT_WRITE
 138 #undef CONFIG_CMD_EXT4
 139 #undef CONFIG_CMD_FS_GENERIC
 140
 141 /* BOOTP/DHCP options */
 142 #define CONFIG_BOOTP_SUBNETMASK
 143 #define CONFIG_BOOTP_GATEWAY
 144 #define CONFIG_BOOTP_HOSTNAME
 145 #define CONFIG_BOOTP_NISDOMAIN
 146 #define CONFIG_BOOTP_BOOTPATH
 147 #define CONFIG_BOOTP_BOOTFILESIZE
 148 #define CONFIG_BOOTP_DNS
 149 #define CONFIG_BOOTP_DNS2
 150 #define CONFIG_BOOTP_SEND_HOSTNAME
 151 #define CONFIG_BOOTP_NTPSERVER
 152 #define CONFIG_BOOTP_TIMEOFFSET
 153 #undef CONFIG_BOOTP_VENDOREX
 154
 155 /* Environment information */
 156 #define CONFIG_EXTRA_ENV_SETTINGS \
 157         "loadaddr=0x82000000\0" \
 158         "console=ttyO2,115200n8\0" \
 159         "mmcdev=0\0" \
 160         "vram=12M\0" \
 161         "dvimode=1024x768MR-16@60\0" \
 162         "defaultdisplay=dvi\0" \
 163         "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
 164         "kernelopts=rw\0" \
 165         "commonargs=" \
 166                 "setenv bootargs console=${console} " \
 167                 "vram=${vram} " \
 168                 "omapfb.mode=dvi:${dvimode} " \
 169                 "omapdss.def_disp=${defaultdisplay}\0" \
 170         "mmcargs=" \
 171                 "run commonargs; " \
 172                 "setenv bootargs ${bootargs} " \
 173                 "root=/dev/mmcblk0p2 " \
 174                 "rootwait " \
 175                 "${kernelopts}\0" \
 176         "nandargs=" \
 177                 "run commonargs; " \
 178                 "setenv bootargs ${bootargs} " \
 179                 "omapfb.mode=dvi:${dvimode} " \
 180                 "omapdss.def_disp=${defaultdisplay} " \
 181                 "root=/dev/mtdblock4 " \
 182                 "rootfstype=jffs2 " \
 183                 "${kernelopts}\0" \
 184         "netargs=" \
 185                 "run commonargs; " \
 186                 "setenv bootargs ${bootargs} " \
 187                 "root=/dev/nfs " \
 188                 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
 189                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
 190                 "${kernelopts} " \
 191                 "dnsip1=${dnsip} " \
 192                 "dnsip2=${dnsip2}\0" \
 193         "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 194         "bootscript=echo Running bootscript from mmc ...; " \
 195                 "source ${loadaddr}\0" \
 196         "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 197         "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
 198         "mmcboot=echo Booting from mmc ...; " \
 199                 "run mmcargs; " \
 200                 "bootm ${loadaddr}\0" \
 201         "nandboot=echo Booting from nand ...; " \
 202                 "run nandargs; " \
 203                 "nand read ${loadaddr} 280000 400000; " \
 204                 "bootm ${loadaddr}\0" \
 205         "netboot=echo Booting from network ...; " \
 206                 "dhcp ${loadaddr}; " \
 207                 "run netargs; " \
 208                 "bootm ${loadaddr}\0" \
 209         "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \
 210                         "if run loadbootscript; then " \
 211                                 "run bootscript; " \
 212                         "else " \
 213                                 "if run loaduimage; then " \
 214                                         "run mmcboot; " \
 215                                 "else run nandboot; " \
 216                                 "fi; " \
 217                         "fi; " \
 218                 "else run nandboot; fi\0"
 219
 220
 221 #define CONFIG_BOOTCOMMAND "run autoboot"
 222
 223 /* Boot Argument Buffer Size */
 224 #define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0 + 0x07000000)
 225 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_MEMTEST_START + \
 226                                         0x01000000) /* 16MB */
 227
 228 /*
 229  * OMAP3 has 12 GP timers, they can be driven by the system clock
 230  * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 231  * This rate is divided by a local divisor.
 232  */
 233 #define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 234
 235 /* NAND and environment organization  */
 236 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 2 sectors */
 237
 238 #define CONFIG_ENV_IS_IN_NAND           1
 239 #define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 240
 241 #define CONFIG_ENV_OFFSET               SMNAND_ENV_OFFSET
 242
 243 /* SRAM config */
 244 #define CONFIG_SYS_SRAM_START              0x40200000
 245 #define CONFIG_SYS_SRAM_SIZE               0x10000
 246
 247 /* Defines for SPL */
 248 #define CONFIG_SPL_NAND_SIMPLE
 249
 250 #define CONFIG_SPL_POWER_SUPPORT
 251 #define CONFIG_SPL_LDSCRIPT             "$(CPUDIR)/omap-common/u-boot-spl.lds"
 252 #undef CONFIG_SPL_MTD_SUPPORT
 253
 254 #define CONFIG_SPL_TEXT_BASE            0x40200000 /*CONFIG_SYS_SRAM_START*/
 255 #define CONFIG_SPL_MAX_SIZE             (54 * 1024)     /* 8 KB for stack */
 256 #undef CONFIG_SPL_STACK
 257 #define CONFIG_SPL_STACK                LOW_LEVEL_SRAM_STACK
 258
 259 /* NAND boot config */
 260 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT  16
 261 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 262 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 263 #define CONFIG_SYS_NAND_PAGE_SIZE       2048
 264 #define CONFIG_SYS_NAND_OOBSIZE         64
 265 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128*1024)
 266 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 267 #define CONFIG_SYS_NAND_ECCPOS          {2, 3, 4, 5, 6, 7, 8, 9,\
 268                                                 10, 11, 12, 13}
 269
 270 #define CONFIG_SYS_NAND_ECCSIZE         512
 271 #define CONFIG_SYS_NAND_ECCBYTES        3
 272 #define CONFIG_NAND_OMAP_ECCSCHEME      OMAP_ECC_HAM1_CODE_HW
 273
 274 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x80000
 275 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x200000
 276
 277 /* SPL OS boot options */
 278 #define CONFIG_CMD_SPL_WRITE_SIZE       0x400 /* 1024 byte */
 279 #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\
 280                                         0x400000)
 281 #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000
 282
 283 #undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR
 284 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR
 285 #undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS
 286 #define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */
 287 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR   0x8   /* address 0x1000 */
 288 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS  8     /* 4KB */
 289
 290 #define CONFIG_SYS_SPL_ARGS_ADDR        (PHYS_SDRAM_1 + 0x100)
 291
 292 #endif /* __CONFIG_H */