include/configs/edminiv2.h

   1 /*
   2  * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
   3  *
   4  * Based on original Kirkwood support which is
   5  * (C) Copyright 2009
   6  * Marvell Semiconductor <www.marvell.com>
   7  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #ifndef _CONFIG_EDMINIV2_H
  13 #define _CONFIG_EDMINIV2_H
  14
  15 /*
  16  * SPL
  17  */
  18
  19 #define CONFIG_SPL_FRAMEWORK
  20 #define CONFIG_SPL_TEXT_BASE            0xffff0000
  21 #define CONFIG_SPL_MAX_SIZE             0x0000fff0
  22 #define CONFIG_SPL_STACK                0x00020000
  23 #define CONFIG_SPL_BSS_START_ADDR       0x00020000
  24 #define CONFIG_SPL_BSS_MAX_SIZE         0x0001ffff
  25 #define CONFIG_SYS_SPL_MALLOC_START     0x00040000
  26 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x0001ffff
  27 #define CONFIG_SYS_UBOOT_BASE           0xfff90000
  28 #define CONFIG_SYS_UBOOT_START          0x00800000
  29 #define CONFIG_SYS_TEXT_BASE            0x00800000
  30
  31 /*
  32  * High Level Configuration Options (easy to change)
  33  */
  34
  35 #define CONFIG_MARVELL          1
  36 #define CONFIG_FEROCEON         1       /* CPU Core subversion */
  37 #define CONFIG_88F5182          1       /* SOC Name */
  38 #define CONFIG_MACH_EDMINIV2    1       /* Machine type */
  39
  40 #include <asm/arch/orion5x.h>
  41 /*
  42  * CLKs configurations
  43  */
  44
  45 /*
  46  * Board-specific values for Orion5x MPP low level init:
  47  * - MPPs 12 to 15 are SATA LEDs (mode 5)
  48  * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
  49  *   MPP16 to MPP19, mode 0 for others
  50  */
  51
  52 #define ORION5X_MPP0_7          0x00000003
  53 #define ORION5X_MPP8_15         0x55550000
  54 #define ORION5X_MPP16_23        0x00005555
  55
  56 /*
  57  * Board-specific values for Orion5x GPIO low level init:
  58  * - GPIO3 is input (RTC interrupt)
  59  * - GPIO16 is Power LED control (0 = on, 1 = off)
  60  * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
  61  * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
  62  * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
  63  * - GPIO22 is SATA disk power status ()
  64  * - GPIO23 is supply status for SATA disk ()
  65  * - GPIO24 is supply control for board (write 1 to power off)
  66  * Last GPIO is 25, further bits are supposed to be 0.
  67  * Enable mask has ones for INPUT, 0 for OUTPUT.
  68  * Default is LED ON, board ON :)
  69  */
  70
  71 #define ORION5X_GPIO_OUT_ENABLE         0xfef4f0ca
  72 #define ORION5X_GPIO_OUT_VALUE          0x00000000
  73 #define ORION5X_GPIO_IN_POLARITY        0x000000d0
  74
  75 /*
  76  * NS16550 Configuration
  77  */
  78
  79 #define CONFIG_SYS_NS16550_SERIAL
  80 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  81 #define CONFIG_SYS_NS16550_CLK          CONFIG_SYS_TCLK
  82 #define CONFIG_SYS_NS16550_COM1         ORION5X_UART0_BASE
  83
  84 /*
  85  * Serial Port configuration
  86  * The following definitions let you select what serial you want to use
  87  * for your console driver.
  88  */
  89
  90 #define CONFIG_CONS_INDEX       1       /*Console on UART0 */
  91 #define CONFIG_SYS_BAUDRATE_TABLE \
  92         { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
  93
  94 /*
  95  * FLASH configuration
  96  */
  97
  98 #define CONFIG_SYS_FLASH_CFI
  99 #define CONFIG_FLASH_CFI_DRIVER
 100 #define CONFIG_SYS_MAX_FLASH_BANKS      1  /* max num of flash banks       */
 101 #define CONFIG_SYS_MAX_FLASH_SECT       11 /* max num of sects on one chip */
 102 #define CONFIG_SYS_FLASH_BASE           0xfff80000
 103
 104 /* auto boot */
 105
 106 /*
 107  * For booting Linux, the board info and command line data
 108  * have to be in the first 8 MB of memory, since this is
 109  * the maximum mapped by the Linux kernel during initialization.
 110  */
 111 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs  */
 112 #define CONFIG_INITRD_TAG       1       /* enable INITRD tag */
 113 #define CONFIG_SETUP_MEMORY_TAGS 1      /* enable memory tag */
 114
 115 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buff Size */
 116 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE \
 117                 +sizeof(CONFIG_SYS_PROMPT) + 16)        /* Print Buff */
 118 /*
 119  * Commands configuration
 120  */
 121
 122 /*
 123  * Network
 124  */
 125
 126 #ifdef CONFIG_CMD_NET
 127 #define CONFIG_MVGBE                            /* Enable Marvell GbE Driver */
 128 #define CONFIG_MVGBE_PORTS      {1}             /* enable port 0 only */
 129 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION     /* don't randomize MAC */
 130 #define CONFIG_PHY_BASE_ADR     0x8
 131 #define CONFIG_RESET_PHY_R      /* use reset_phy() to init mv8831116 PHY */
 132 #define CONFIG_NETCONSOLE       /* include NetConsole support   */
 133 #define CONFIG_MII              /* expose smi ove miiphy interface */
 134 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
 135 #define CONFIG_ENV_OVERWRITE    /* ethaddr can be reprogrammed */
 136 #endif
 137
 138 /*
 139  * IDE
 140  */
 141 #ifdef CONFIG_IDE
 142 #define __io
 143 #define CONFIG_IDE_PREINIT
 144 /* ED Mini V has an IDE-compatible SATA connector for port 1 */
 145 #define CONFIG_MVSATA_IDE
 146 #define CONFIG_MVSATA_IDE_USE_PORT1
 147 /* Needs byte-swapping for ATA data register */
 148 #define CONFIG_IDE_SWAP_IO
 149 /* Data, registers and alternate blocks are at the same offset */
 150 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0100)
 151 #define CONFIG_SYS_ATA_REG_OFFSET       (0x0100)
 152 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x0100)
 153 /* Each 8-bit ATA register is aligned to a 4-bytes address */
 154 #define CONFIG_SYS_ATA_STRIDE           4
 155 /* Controller supports 48-bits LBA addressing */
 156 #define CONFIG_LBA48
 157 /* A single bus, a single device */
 158 #define CONFIG_SYS_IDE_MAXBUS           1
 159 #define CONFIG_SYS_IDE_MAXDEVICE        1
 160 /* ATA registers base is at SATA controller base */
 161 #define CONFIG_SYS_ATA_BASE_ADDR        ORION5X_SATA_BASE
 162 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */
 163 #define CONFIG_SYS_ATA_IDE0_OFFSET      ORION5X_SATA_PORT1_OFFSET
 164 /* end of IDE defines */
 165 #endif /* CMD_IDE */
 166
 167 /*
 168  * Common USB/EHCI configuration
 169  */
 170 #ifdef CONFIG_CMD_USB
 171 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
 172 #define CONFIG_SUPPORT_VFAT
 173 #endif /* CONFIG_CMD_USB */
 174
 175 /*
 176  * I2C related stuff
 177  */
 178 #ifdef CONFIG_CMD_I2C
 179 #define CONFIG_SYS_I2C
 180 #define CONFIG_SYS_I2C_MVTWSI
 181 #define CONFIG_I2C_MVTWSI_BASE0         ORION5X_TWSI_BASE
 182 #define CONFIG_SYS_I2C_SLAVE            0x0
 183 #define CONFIG_SYS_I2C_SPEED            100000
 184 #endif
 185
 186 /*
 187  *  Environment variables configurations
 188  */
 189 #define CONFIG_ENV_SECT_SIZE            0x2000  /* 16K */
 190 #define CONFIG_ENV_SIZE                 0x2000
 191 #define CONFIG_ENV_OFFSET               0x4000  /* env starts here */
 192
 193 /*
 194  * Size of malloc() pool
 195  */
 196 #define CONFIG_SYS_MALLOC_LEN   (1024 * 256) /* 256kB for malloc() */
 197
 198 /*
 199  * Other required minimal configurations
 200  */
 201 #define CONFIG_ARCH_CPU_INIT            /* call arch_cpu_init() */
 202 #define CONFIG_NR_DRAM_BANKS            1
 203
 204 #define CONFIG_SYS_LOAD_ADDR            0x00800000
 205 #define CONFIG_SYS_MEMTEST_START        0x00400000
 206 #define CONFIG_SYS_MEMTEST_END          0x007fffff
 207 #define CONFIG_SYS_RESET_ADDRESS        0xffff0000
 208 #define CONFIG_SYS_MAXARGS              16
 209
 210 /* Enable command line editing */
 211 #define CONFIG_CMDLINE_EDITING
 212
 213 /* provide extensive help */
 214 #define CONFIG_SYS_LONGHELP
 215
 216 /* additions for new relocation code, must be added to all boards */
 217 #define CONFIG_SYS_SDRAM_BASE           0
 218 #define CONFIG_SYS_INIT_SP_ADDR \
 219         (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
 220
 221 #endif /* _CONFIG_EDMINIV2_H */