include/configs/edminiv2.h

   1 /*
   2  * Copyright (C) 2010 Albert ARIBAUD <albert.aribaud@free.fr>
   3  *
   4  * Based on original Kirkwood support which is
   5  * (C) Copyright 2009
   6  * Marvell Semiconductor <www.marvell.com>
   7  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  25  * MA 02110-1301 USA
  26  */
  27
  28 #ifndef _CONFIG_EDMINIV2_H
  29 #define _CONFIG_EDMINIV2_H
  30
  31 /*
  32  * Version number information
  33  */
  34
  35 #define CONFIG_IDENT_STRING     " EDMiniV2"
  36
  37 /*
  38  * High Level Configuration Options (easy to change)
  39  */
  40
  41 #define CONFIG_MARVELL          1
  42 #define CONFIG_ARM926EJS        1       /* Basic Architecture */
  43 #define CONFIG_FEROCEON         1       /* CPU Core subversion */
  44 #define CONFIG_ORION5X          1       /* SOC Family Name */
  45 #define CONFIG_88F5182          1       /* SOC Name */
  46 #define CONFIG_MACH_EDMINIV2    1       /* Machine type */
  47
  48 /*
  49  * CLKs configurations
  50  */
  51
  52 #define CONFIG_SYS_HZ           1000
  53
  54 /*
  55  * Board-specific values for Orion5x MPP low level init:
  56  * - MPPs 12 to 15 are SATA LEDs (mode 5)
  57  * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
  58  *   MPP16 to MPP19, mode 0 for others
  59  */
  60
  61 #define ORION5X_MPP0_7          0x00000003
  62 #define ORION5X_MPP8_15         0x55550000
  63 #define ORION5X_MPP16_23        0x00005555
  64
  65 /*
  66  * Board-specific values for Orion5x GPIO low level init:
  67  * - GPIO3 is input (RTC interrupt)
  68  * - GPIO16 is Power LED control (0 = on, 1 = off)
  69  * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
  70  * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
  71  * - Last GPIO is 26, further bits are supposed to be 0.
  72  * Enable mask has ones for INPUT, 0 for OUTPUT.
  73  * Default is LED ON.
  74  */
  75
  76 #define ORION5X_GPIO_OUT_ENABLE 0x03fcffff
  77 #define ORION5X_GPIO_OUT_VALUE  0x03fcffff
  78
  79 /*
  80  * NS16550 Configuration
  81  */
  82
  83 #define CONFIG_SYS_NS16550
  84 #define CONFIG_SYS_NS16550_SERIAL
  85 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  86 #define CONFIG_SYS_NS16550_CLK          CONFIG_SYS_TCLK
  87 #define CONFIG_SYS_NS16550_COM1         ORION5X_UART0_BASE
  88
  89 /*
  90  * Serial Port configuration
  91  * The following definitions let you select what serial you want to use
  92  * for your console driver.
  93  */
  94
  95 #define CONFIG_CONS_INDEX       1       /*Console on UART0 */
  96 #define CONFIG_BAUDRATE                 115200
  97 #define CONFIG_SYS_BAUDRATE_TABLE \
  98         { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
  99
 100 /*
 101  * FLASH configuration
 102  */
 103
 104 #define CONFIG_SYS_FLASH_CFI
 105 #define CONFIG_FLASH_CFI_DRIVER
 106 #define CONFIG_FLASH_CFI_LEGACY
 107 #define CONFIG_SYS_MAX_FLASH_BANKS      1  /* max num of flash banks       */
 108 #define CONFIG_SYS_MAX_FLASH_SECT       11 /* max num of sects on one chip */
 109 #define CONFIG_SYS_FLASH_BASE           0xfff80000
 110 #define CONFIG_SYS_FLASH_SECTSZ \
 111         {16384, 8192, 8192, 32768, \
 112          65536, 65536, 65536, 65536, 65536, 65536, 65536}
 113
 114 /* auto boot */
 115 #define CONFIG_BOOTDELAY        3       /* default enable autoboot */
 116
 117 /*
 118  * For booting Linux, the board info and command line data
 119  * have to be in the first 8 MB of memory, since this is
 120  * the maximum mapped by the Linux kernel during initialization.
 121  */
 122 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs  */
 123 #define CONFIG_INITRD_TAG       1       /* enable INITRD tag */
 124 #define CONFIG_SETUP_MEMORY_TAGS 1      /* enable memory tag */
 125
 126 #define CONFIG_SYS_PROMPT       "EDMiniV2> "    /* Command Prompt */
 127 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buff Size */
 128 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE \
 129                 +sizeof(CONFIG_SYS_PROMPT) + 16)        /* Print Buff */
 130 /*
 131  * Commands configuration - using default command set for now
 132  */
 133 #include <config_cmd_default.h>
 134 #define CONFIG_CMD_IDE
 135 #define CONFIG_CMD_I2C
 136
 137 /*
 138  * Network
 139  */
 140
 141 #ifdef CONFIG_CMD_NET
 142 #define CONFIG_MVGBE                            /* Enable Marvell GbE Driver */
 143 #define CONFIG_MVGBE_PORTS      {1}             /* enable port 0 only */
 144 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION     /* don't randomize MAC */
 145 #define CONFIG_PHY_BASE_ADR     0x8
 146 #define CONFIG_RESET_PHY_R      /* use reset_phy() to init mv8831116 PHY */
 147 #define CONFIG_NETCONSOLE       /* include NetConsole support   */
 148 #define CONFIG_NET_MULTI        /* specify more that one ports available */
 149 #define CONFIG_MII              /* expose smi ove miiphy interface */
 150 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
 151 #define CONFIG_ENV_OVERWRITE    /* ethaddr can be reprogrammed */
 152 #endif
 153
 154 /*
 155  * IDE
 156  */
 157 #ifdef CONFIG_CMD_IDE
 158 #define __io
 159 #define CONFIG_IDE_PREINIT
 160 #define CONFIG_DOS_PARTITION
 161 #define CONFIG_CMD_EXT2
 162 /* ED Mini V has an IDE-compatible SATA connector for port 1 */
 163 #define CONFIG_MVSATA_IDE
 164 #define CONFIG_MVSATA_IDE_USE_PORT1
 165 /* Needs byte-swapping for ATA data register */
 166 #define CONFIG_IDE_SWAP_IO
 167 /* Data, registers and alternate blocks are at the same offset */
 168 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0100)
 169 #define CONFIG_SYS_ATA_REG_OFFSET       (0x0100)
 170 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x0100)
 171 /* Each 8-bit ATA register is aligned to a 4-bytes address */
 172 #define CONFIG_SYS_ATA_STRIDE           4
 173 /* Controller supports 48-bits LBA addressing */
 174 #define CONFIG_LBA48
 175 /* A single bus, a single device */
 176 #define CONFIG_SYS_IDE_MAXBUS           1
 177 #define CONFIG_SYS_IDE_MAXDEVICE        1
 178 /* ATA registers base is at SATA controller base */
 179 #define CONFIG_SYS_ATA_BASE_ADDR        ORION5X_SATA_BASE
 180 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */
 181 #define CONFIG_SYS_ATA_IDE0_OFFSET      ORION5X_SATA_PORT1_OFFSET
 182 /* end of IDE defines */
 183 #endif /* CMD_IDE */
 184
 185 /*
 186  * I2C related stuff
 187  */
 188 #ifdef CONFIG_CMD_I2C
 189 #define CONFIG_I2C_MVTWSI
 190 #define CONFIG_I2C_MVTWSI_BASE          ORION5X_TWSI_BASE
 191 #define CONFIG_SYS_I2C_SLAVE            0x0
 192 #define CONFIG_SYS_I2C_SPEED            100000
 193 #endif
 194
 195 /*
 196  *  Environment variables configurations
 197  */
 198 #define CONFIG_ENV_IS_IN_FLASH          1
 199 #define CONFIG_ENV_SECT_SIZE            0x2000  /* 16K */
 200 #define CONFIG_ENV_SIZE                 0x2000
 201 #define CONFIG_ENV_OFFSET               0x4000  /* env starts here */
 202
 203 /*
 204  * Size of malloc() pool
 205  */
 206 #define CONFIG_SYS_MALLOC_LEN   (1024 * 128) /* 128kB for malloc() */
 207 /* size in bytes reserved for initial data */
 208
 209 /*
 210  * Other required minimal configurations
 211  */
 212 #define CONFIG_CONSOLE_INFO_QUIET       /* some code reduction */
 213 #define CONFIG_ARCH_CPU_INIT            /* call arch_cpu_init() */
 214 #define CONFIG_ARCH_MISC_INIT           /* call arch_misc_init() */
 215 #define CONFIG_DISPLAY_CPUINFO          /* Display cpu info */
 216 #define CONFIG_NR_DRAM_BANKS            1
 217
 218 #define CONFIG_STACKSIZE                0x00100000
 219 #define CONFIG_SYS_LOAD_ADDR            0x00800000
 220 #define CONFIG_SYS_MEMTEST_START        0x00400000
 221 #define CONFIG_SYS_MEMTEST_END          0x007fffff
 222 #define CONFIG_SYS_RESET_ADDRESS        0xffff0000
 223 #define CONFIG_SYS_MAXARGS              16
 224
 225 /* additions for new relocation code, must be added to all boards */
 226 #define CONFIG_SYS_SDRAM_BASE           0
 227 #define CONFIG_SYS_INIT_SP_ADDR \
 228         (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
 229
 230 #endif /* _CONFIG_EDMINIV2_H */