include/configs/edminiv2.h

   1 /*
   2  * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
   3  *
   4  * Based on original Kirkwood support which is
   5  * (C) Copyright 2009
   6  * Marvell Semiconductor <www.marvell.com>
   7  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  25  * MA 02110-1301 USA
  26  */
  27
  28 #ifndef _CONFIG_EDMINIV2_H
  29 #define _CONFIG_EDMINIV2_H
  30
  31 /*
  32  * Version number information
  33  */
  34
  35 #define CONFIG_IDENT_STRING     " EDMiniV2"
  36
  37 /*
  38  * High Level Configuration Options (easy to change)
  39  */
  40
  41 #define CONFIG_MARVELL          1
  42 #define CONFIG_ARM926EJS        1       /* Basic Architecture */
  43 #define CONFIG_FEROCEON         1       /* CPU Core subversion */
  44 #define CONFIG_ORION5X          1       /* SOC Family Name */
  45 #define CONFIG_88F5182          1       /* SOC Name */
  46 #define CONFIG_MACH_EDMINIV2    1       /* Machine type */
  47
  48 #include <asm/arch/orion5x.h>
  49 /*
  50  * CLKs configurations
  51  */
  52
  53 #define CONFIG_SYS_HZ           1000
  54
  55 /*
  56  * Board-specific values for Orion5x MPP low level init:
  57  * - MPPs 12 to 15 are SATA LEDs (mode 5)
  58  * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
  59  *   MPP16 to MPP19, mode 0 for others
  60  */
  61
  62 #define ORION5X_MPP0_7          0x00000003
  63 #define ORION5X_MPP8_15         0x55550000
  64 #define ORION5X_MPP16_23        0x00005555
  65
  66 /*
  67  * Board-specific values for Orion5x GPIO low level init:
  68  * - GPIO3 is input (RTC interrupt)
  69  * - GPIO16 is Power LED control (0 = on, 1 = off)
  70  * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
  71  * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
  72  * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
  73  * - GPIO22 is SATA disk power status ()
  74  * - GPIO23 is supply status for SATA disk ()
  75  * - GPIO24 is supply control for board (write 1 to power off)
  76  * Last GPIO is 25, further bits are supposed to be 0.
  77  * Enable mask has ones for INPUT, 0 for OUTPUT.
  78  * Default is LED ON, board ON :)
  79  */
  80
  81 #define ORION5X_GPIO_OUT_ENABLE         0xfef4f0ca
  82 #define ORION5X_GPIO_OUT_VALUE          0x00000000
  83 #define ORION5X_GPIO_IN_POLARITY        0x000000d0
  84
  85 /*
  86  * NS16550 Configuration
  87  */
  88
  89 #define CONFIG_SYS_NS16550
  90 #define CONFIG_SYS_NS16550_SERIAL
  91 #define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  92 #define CONFIG_SYS_NS16550_CLK          CONFIG_SYS_TCLK
  93 #define CONFIG_SYS_NS16550_COM1         ORION5X_UART0_BASE
  94
  95 /*
  96  * Serial Port configuration
  97  * The following definitions let you select what serial you want to use
  98  * for your console driver.
  99  */
 100
 101 #define CONFIG_CONS_INDEX       1       /*Console on UART0 */
 102 #define CONFIG_BAUDRATE                 115200
 103 #define CONFIG_SYS_BAUDRATE_TABLE \
 104         { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
 105
 106 /*
 107  * FLASH configuration
 108  */
 109
 110 #define CONFIG_SYS_FLASH_CFI
 111 #define CONFIG_FLASH_CFI_DRIVER
 112 #define CONFIG_FLASH_CFI_LEGACY
 113 #define CONFIG_SYS_MAX_FLASH_BANKS      1  /* max num of flash banks       */
 114 #define CONFIG_SYS_MAX_FLASH_SECT       11 /* max num of sects on one chip */
 115 #define CONFIG_SYS_FLASH_BASE           0xfff80000
 116 #define CONFIG_SYS_FLASH_SECTSZ \
 117         {16384, 8192, 8192, 32768, \
 118          65536, 65536, 65536, 65536, 65536, 65536, 65536}
 119
 120 /* auto boot */
 121 #define CONFIG_BOOTDELAY        3       /* default enable autoboot */
 122
 123 /*
 124  * For booting Linux, the board info and command line data
 125  * have to be in the first 8 MB of memory, since this is
 126  * the maximum mapped by the Linux kernel during initialization.
 127  */
 128 #define CONFIG_CMDLINE_TAG      1       /* enable passing of ATAGs  */
 129 #define CONFIG_INITRD_TAG       1       /* enable INITRD tag */
 130 #define CONFIG_SETUP_MEMORY_TAGS 1      /* enable memory tag */
 131
 132 #define CONFIG_SYS_PROMPT       "EDMiniV2> "    /* Command Prompt */
 133 #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buff Size */
 134 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE \
 135                 +sizeof(CONFIG_SYS_PROMPT) + 16)        /* Print Buff */
 136 /*
 137  * Commands configuration - using default command set for now
 138  */
 139 #include <config_cmd_default.h>
 140 #define CONFIG_CMD_IDE
 141 #define CONFIG_CMD_I2C
 142 #define CONFIG_CMD_USB
 143
 144 /*
 145  * Network
 146  */
 147
 148 #ifdef CONFIG_CMD_NET
 149 #define CONFIG_MVGBE                            /* Enable Marvell GbE Driver */
 150 #define CONFIG_MVGBE_PORTS      {1}             /* enable port 0 only */
 151 #define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION     /* don't randomize MAC */
 152 #define CONFIG_PHY_BASE_ADR     0x8
 153 #define CONFIG_RESET_PHY_R      /* use reset_phy() to init mv8831116 PHY */
 154 #define CONFIG_NETCONSOLE       /* include NetConsole support   */
 155 #define CONFIG_MII              /* expose smi ove miiphy interface */
 156 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
 157 #define CONFIG_ENV_OVERWRITE    /* ethaddr can be reprogrammed */
 158 #endif
 159
 160 /*
 161  * IDE
 162  */
 163 #ifdef CONFIG_CMD_IDE
 164 #define __io
 165 #define CONFIG_IDE_PREINIT
 166 #define CONFIG_DOS_PARTITION
 167 #define CONFIG_CMD_EXT2
 168 /* ED Mini V has an IDE-compatible SATA connector for port 1 */
 169 #define CONFIG_MVSATA_IDE
 170 #define CONFIG_MVSATA_IDE_USE_PORT1
 171 /* Needs byte-swapping for ATA data register */
 172 #define CONFIG_IDE_SWAP_IO
 173 /* Data, registers and alternate blocks are at the same offset */
 174 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0100)
 175 #define CONFIG_SYS_ATA_REG_OFFSET       (0x0100)
 176 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x0100)
 177 /* Each 8-bit ATA register is aligned to a 4-bytes address */
 178 #define CONFIG_SYS_ATA_STRIDE           4
 179 /* Controller supports 48-bits LBA addressing */
 180 #define CONFIG_LBA48
 181 /* A single bus, a single device */
 182 #define CONFIG_SYS_IDE_MAXBUS           1
 183 #define CONFIG_SYS_IDE_MAXDEVICE        1
 184 /* ATA registers base is at SATA controller base */
 185 #define CONFIG_SYS_ATA_BASE_ADDR        ORION5X_SATA_BASE
 186 /* ATA bus 0 is orion5x port 1 on ED Mini V2 */
 187 #define CONFIG_SYS_ATA_IDE0_OFFSET      ORION5X_SATA_PORT1_OFFSET
 188 /* end of IDE defines */
 189 #endif /* CMD_IDE */
 190
 191 /*
 192  * Common USB/EHCI configuration
 193  */
 194 #ifdef CONFIG_CMD_USB
 195 #define CONFIG_USB_EHCI         /* Enable EHCI USB support */
 196 #define CONFIG_USB_EHCI_MARVELL
 197 #define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
 198 #define CONFIG_USB_STORAGE
 199 #define CONFIG_DOS_PARTITION
 200 #define CONFIG_ISO_PARTITION
 201 #define CONFIG_SUPPORT_VFAT
 202 #endif /* CONFIG_CMD_USB */
 203
 204 /*
 205  * I2C related stuff
 206  */
 207 #ifdef CONFIG_CMD_I2C
 208 #define CONFIG_I2C_MVTWSI
 209 #define CONFIG_I2C_MVTWSI_BASE          ORION5X_TWSI_BASE
 210 #define CONFIG_SYS_I2C_SLAVE            0x0
 211 #define CONFIG_SYS_I2C_SPEED            100000
 212 #endif
 213
 214 /*
 215  *  Environment variables configurations
 216  */
 217 #define CONFIG_ENV_IS_IN_FLASH          1
 218 #define CONFIG_ENV_SECT_SIZE            0x2000  /* 16K */
 219 #define CONFIG_ENV_SIZE                 0x2000
 220 #define CONFIG_ENV_OFFSET               0x4000  /* env starts here */
 221
 222 /*
 223  * Size of malloc() pool
 224  */
 225 #define CONFIG_SYS_MALLOC_LEN   (1024 * 256) /* 256kB for malloc() */
 226
 227 /*
 228  * Other required minimal configurations
 229  */
 230 #define CONFIG_CONSOLE_INFO_QUIET       /* some code reduction */
 231 #define CONFIG_ARCH_CPU_INIT            /* call arch_cpu_init() */
 232 #define CONFIG_ARCH_MISC_INIT           /* call arch_misc_init() */
 233 #define CONFIG_DISPLAY_CPUINFO          /* Display cpu info */
 234 #define CONFIG_NR_DRAM_BANKS            1
 235
 236 #define CONFIG_SYS_LOAD_ADDR            0x00800000
 237 #define CONFIG_SYS_MEMTEST_START        0x00400000
 238 #define CONFIG_SYS_MEMTEST_END          0x007fffff
 239 #define CONFIG_SYS_RESET_ADDRESS        0xffff0000
 240 #define CONFIG_SYS_MAXARGS              16
 241
 242 /* Use the HUSH parser */
 243 #define CONFIG_SYS_HUSH_PARSER
 244
 245 /* Enable command line editing */
 246 #define CONFIG_CMDLINE_EDITING
 247
 248 /* provide extensive help */
 249 #define CONFIG_SYS_LONGHELP
 250
 251 /* additions for new relocation code, must be added to all boards */
 252 #define CONFIG_SYS_SDRAM_BASE           0
 253 #define CONFIG_SYS_INIT_SP_ADDR \
 254         (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
 255
 256 #endif /* _CONFIG_EDMINIV2_H */