include/configs/ep8260.h

   1 /*
   2  * (C) Copyright 2002
   3  * Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
   4  *
   5  * This file is based on similar values for other boards found in other
   6  * U-Boot config files, and some that I found in the EP8260 manual.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  *
  30  * "EP8260 H, V.1.1"
  31  *      - 64M 60x Bus SDRAM
  32  *      - 32M Local Bus SDRAM
  33  *      - 16M Flash (4 x AM29DL323DB90WDI)
  34  *      - 128k NVRAM with RTC
  35  *
  36  * "EP8260 H2, V.1.3" (CFG_EP8260_H2)
  37  *      - 300MHz/133MHz/66MHz
  38  *      - 64M 60x Bus SDRAM
  39  *      - 32M Local Bus SDRAM
  40  *      - 32M Flash
  41  *      - 128k NVRAM with RTC
  42  */
  43
  44 #ifndef __CONFIG_H
  45 #define __CONFIG_H
  46
  47 /* Define this to enable support the EP8260 H2 version */
  48 #define CFG_EP8260_H2   1
  49 /* #undef CFG_EP8260_H2  */
  50
  51 #define CONFIG_CPM2             1       /* Has a CPM2 */
  52
  53 /* What is the oscillator's (UX2) frequency in Hz? */
  54 #define CONFIG_8260_CLKIN  (66 * 1000 * 1000)
  55
  56 /*-----------------------------------------------------------------------
  57  * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
  58  *-----------------------------------------------------------------------
  59  * What should MODCK_H be? It is dependent on the oscillator
  60  * frequency, MODCK[1-3], and desired CPM and core frequencies.
  61  * Here are some example values (all frequencies are in MHz):
  62  *
  63  * MODCK_H   MODCK[1-3]  Osc    CPM    Core
  64  * -------   ----------  ---    ---    ----
  65  * 0x2       0x2         33     133    133
  66  * 0x2       0x3         33     133    166
  67  * 0x2       0x4         33     133    200
  68  * 0x2       0x5         33     133    233
  69  * 0x2       0x6         33     133    266
  70  *
  71  * 0x5       0x5         66     133    133
  72  * 0x5       0x6         66     133    166
  73  * 0x5       0x7         66     133    200 *
  74  * 0x6       0x0         66     133    233
  75  * 0x6       0x1         66     133    266
  76  * 0x6       0x2         66     133    300
  77  */
  78 #ifdef CFG_EP8260_H2
  79 #define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
  80 #else
  81 #define CFG_SBC_MODCK_H  (HRCW_MODCK_H0110)
  82 #endif
  83
  84 /* Define this if you want to boot from 0x00000100. If you don't define
  85  * this, you will need to program the bootloader to 0xfff00000, and
  86  * get the hardware reset config words at 0xfe000000. The simplest
  87  * way to do that is to program the bootloader at both addresses.
  88  * It is suggested that you just let U-Boot live at 0x00000000.
  89  */
  90 /* #define CFG_SBC_BOOT_LOW 1 */        /* only for HRCW */
  91 /* #undef CFG_SBC_BOOT_LOW */
  92
  93 /* The reset command will not work as expected if the reset address does
  94  * not point to the correct address.
  95  */
  96
  97 #define CFG_RESET_ADDRESS       0xFFF00100
  98
  99 /* What should the base address of the main FLASH be and how big is
 100  * it (in MBytes)? This must contain TEXT_BASE from board/ep8260/config.mk
 101  * The main FLASH is whichever is connected to *CS0. U-Boot expects
 102  * this to be the SIMM.
 103  */
 104 #ifdef CFG_EP8260_H2
 105 #define CFG_FLASH0_BASE 0xFE000000
 106 #define CFG_FLASH0_SIZE 32
 107 #else
 108 #define CFG_FLASH0_BASE 0xFF000000
 109 #define CFG_FLASH0_SIZE 16
 110 #endif
 111
 112 /* What should the base address of the secondary FLASH be and how big
 113  * is it (in Mbytes)? The secondary FLASH is whichever is connected
 114  * to *CS6. U-Boot expects this to be the on board FLASH. If you don't
 115  * want it enabled, don't define these constants.
 116  */
 117 #define CFG_FLASH1_BASE 0
 118 #define CFG_FLASH1_SIZE 0
 119 #undef CFG_FLASH1_BASE
 120 #undef CFG_FLASH1_SIZE
 121
 122 /* What should be the base address of SDRAM DIMM (60x bus) and how big is
 123  * it (in Mbytes)?
 124 */
 125 #define CFG_SDRAM0_BASE 0x00000000
 126 #define CFG_SDRAM0_SIZE 64
 127
 128 /* define CFG_LSDRAM if you want to enable the 32M SDRAM on the
 129  * local bus (8260 local bus is NOT cacheable!)
 130 */
 131 /* #define CFG_LSDRAM */
 132 #undef CFG_LSDRAM
 133
 134 #ifdef CFG_LSDRAM
 135 /* What should be the base address of SDRAM DIMM (local bus) and how big is
 136  * it (in Mbytes)?
 137 */
 138   #define CFG_SDRAM1_BASE 0x04000000
 139   #define CFG_SDRAM1_SIZE 32
 140 #else
 141   #define CFG_SDRAM1_BASE 0
 142   #define CFG_SDRAM1_SIZE 0
 143   #undef CFG_SDRAM1_BASE
 144   #undef CFG_SDRAM1_SIZE
 145 #endif /* CFG_LSDRAM */
 146
 147 /* What should be the base address of NVRAM and how big is
 148  * it (in Bytes)
 149  */
 150 #define CFG_NVRAM_BASE_ADDR  0xFA080000
 151 #define CFG_NVRAM_SIZE       (128*1024)-16
 152
 153 /* The RTC is a Dallas DS1556
 154  */
 155 #define CONFIG_RTC_DS1556
 156
 157 /* What should be the base address of the LEDs and switch S0?
 158  * If you don't want them enabled, don't define this.
 159  */
 160 #define CFG_LED_BASE 0x00000000
 161 #undef CFG_LED_BASE
 162
 163 /*
 164  * select serial console configuration
 165  *
 166  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
 167  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
 168  * for SCC).
 169  *
 170  * if CONFIG_CONS_NONE is defined, then the serial console routines must
 171  * defined elsewhere.
 172  */
 173 #define CONFIG_CONS_ON_SMC          /* define if console on SMC */
 174 #undef  CONFIG_CONS_ON_SCC          /* define if console on SCC */
 175 #undef  CONFIG_CONS_NONE            /* define if console on neither */
 176 #define CONFIG_CONS_INDEX    1      /* which SMC/SCC channel for console */
 177
 178 /*
 179  * select ethernet configuration
 180  *
 181  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 182  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 183  * for FCC)
 184  *
 185  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 186  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 187  */
 188 #undef  CONFIG_ETHER_ON_SCC           /* define if ethernet on SCC    */
 189 #define CONFIG_ETHER_ON_FCC           /* define if ethernet on FCC    */
 190 #undef  CONFIG_ETHER_NONE             /* define if ethernet on neither */
 191 #define CONFIG_ETHER_INDEX      3     /* which SCC/FCC channel for ethernet */
 192
 193 #if ( CONFIG_ETHER_INDEX == 3 )
 194
 195 /*
 196  * - Rx-CLK is CLK15
 197  * - Tx-CLK is CLK16
 198  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 199  * - Enable Half Duplex in FSMR
 200  */
 201 # define CFG_CMXFCR_MASK        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 202 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 203
 204 /*
 205  * - RAM for BD/Buffers is on the local Bus (see 28-13)
 206  */
 207 #ifdef CFG_LSDRAM
 208   #define CFG_CPMFCR_RAMTYPE    3
 209 #else /* CFG_LSDRAM */
 210   #define CFG_CPMFCR_RAMTYPE    0
 211 #endif /* CFG_LSDRAM */
 212
 213 /* - Enable Half Duplex in FSMR */
 214 /* # define CFG_FCC_PSMR                (FCC_PSMR_FDE|FCC_PSMR_LPB) */
 215 # define CFG_FCC_PSMR           0
 216
 217 #else /* CONFIG_ETHER_INDEX */
 218 # error "on EP8260 ethernet must be FCC3"
 219 #endif /* CONFIG_ETHER_INDEX */
 220
 221 /*
 222  * select i2c support configuration
 223  *
 224  * Supported configurations are {none, software, hardware} drivers.
 225  * If the software driver is chosen, there are some additional
 226  * configuration items that the driver uses to drive the port pins.
 227  */
 228 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 229 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 230 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 231 #define CFG_I2C_SLAVE           0x7F
 232
 233 /*
 234  * Software (bit-bang) I2C driver configuration
 235  */
 236 #ifdef CONFIG_SOFT_I2C
 237 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 238 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 239 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 240 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 241 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 242                         else    iop->pdat &= ~0x00010000
 243 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 244                         else    iop->pdat &= ~0x00020000
 245 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 246 #endif /* CONFIG_SOFT_I2C */
 247
 248 /* #define CONFIG_RTC_DS174x */
 249
 250 /* Define this to reserve an entire FLASH sector (256 KB) for
 251  * environment variables. Otherwise, the environment will be
 252  * put in the same sector as U-Boot, and changing variables
 253  * will erase U-Boot temporarily
 254  */
 255 #define CFG_ENV_IN_OWN_SECT
 256
 257 /* Define to allow the user to overwrite serial and ethaddr */
 258 #define CONFIG_ENV_OVERWRITE
 259
 260 /* What should the console's baud rate be? */
 261 #ifdef CFG_EP8260_H2
 262 #define CONFIG_BAUDRATE         9600
 263 #else
 264 #define CONFIG_BAUDRATE         115200
 265 #endif
 266
 267 /* Ethernet MAC address */
 268 #define CONFIG_ETHADDR          00:10:EC:00:30:8C
 269
 270 #define CONFIG_IPADDR           192.168.254.130
 271 #define CONFIG_SERVERIP         192.168.254.49
 272
 273 /* Set to a positive value to delay for running BOOTCOMMAND */
 274 #define CONFIG_BOOTDELAY        -1
 275
 276 /* undef this to save memory */
 277 #define CFG_LONGHELP
 278
 279 /* Monitor Command Prompt       */
 280 #define CFG_PROMPT              "=> "
 281
 282 /* Define this variable to enable the "hush" shell (from
 283    Busybox) as command line interpreter, thus enabling
 284    powerful command line syntax like
 285    if...then...else...fi conditionals or `&&' and '||'
 286    constructs ("shell scripts").
 287    If undefined, you get the old, much simpler behaviour
 288    with a somewhat smapper memory footprint.
 289 */
 290 #define CFG_HUSH_PARSER
 291 #define CFG_PROMPT_HUSH_PS2     "> "
 292
 293
 294 /*
 295  * BOOTP options
 296  */
 297 #define CONFIG_BOOTP_BOOTFILESIZE
 298 #define CONFIG_BOOTP_BOOTPATH
 299 #define CONFIG_BOOTP_GATEWAY
 300 #define CONFIG_BOOTP_HOSTNAME
 301
 302
 303 /*
 304  * Command line configuration.
 305  */
 306 #include <config_cmd_all.h>
 307
 308 #undef CONFIG_CMD_BMP
 309 #undef CONFIG_CMD_BSP
 310 #undef CONFIG_CMD_DCR
 311 #undef CONFIG_CMD_DHCP
 312 #undef CONFIG_CMD_DISPLAY
 313 #undef CONFIG_CMD_DOC
 314 #undef CONFIG_CMD_DTT
 315 #undef CONFIG_CMD_EEPROM
 316 #undef CONFIG_CMD_EXT2
 317 #undef CONFIG_CMD_FDC
 318 #undef CONFIG_CMD_FDOS
 319 #undef CONFIG_CMD_HWFLOW
 320 #undef CONFIG_CMD_IDE
 321 #undef CONFIG_CMD_JFFS2
 322 #undef CONFIG_CMD_KGDB
 323 #undef CONFIG_CMD_MII
 324 #undef CONFIG_CMD_MMC
 325 #undef CONFIG_CMD_NAND
 326 #undef CONFIG_CMD_PCI
 327 #undef CONFIG_CMD_PCMCIA
 328 #undef CONFIG_CMD_REISER
 329 #undef CONFIG_CMD_SCSI
 330 #undef CONFIG_CMD_SPI
 331 #undef CONFIG_CMD_UNIVERSE
 332 #undef CONFIG_CMD_USB
 333 #undef CONFIG_CMD_VFD
 334 #undef CONFIG_CMD_XIMG
 335
 336
 337 /* Where do the internal registers live? */
 338 #define CFG_IMMR               0xF0000000
 339 #define CFG_DEFAULT_IMMR       0x00010000
 340
 341 /* Where do the on board registers (CS4) live? */
 342 #define CFG_REGS_BASE          0xFA000000
 343
 344 /*****************************************************************************
 345  *
 346  * You should not have to modify any of the following settings
 347  *
 348  *****************************************************************************/
 349
 350 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU   */
 351 #define CONFIG_EP8260           11      /* on an Embedded Planet EP8260 Board, Rev. 11 */
 352
 353 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
 354
 355 /*
 356  * Miscellaneous configurable options
 357  */
 358 #if defined(CONFIG_CMD_KGDB)
 359 #  define CFG_CBSIZE              1024       /* Console I/O Buffer Size      */
 360 #else
 361 #  define CFG_CBSIZE              256        /* Console I/O Buffer Size      */
 362 #endif
 363
 364 /* Print Buffer Size */
 365 #define CFG_PBSIZE        (CFG_CBSIZE + sizeof(CFG_PROMPT)+16)
 366
 367 #define CFG_MAXARGS       8            /* max number of command args   */
 368
 369 #define CFG_BARGSIZE      CFG_CBSIZE   /* Boot Argument Buffer Size    */
 370
 371 #ifdef CFG_LSDRAM
 372   #define CFG_MEMTEST_START 0x04000000   /* memtest works on  */
 373   #define CFG_MEMTEST_END   0x06000000   /* 64-96 MB in SDRAM */
 374 #else
 375   #define CFG_MEMTEST_START 0x00000000   /* memtest works on  */
 376   #define CFG_MEMTEST_END   0x02000000   /* 0-32 MB in SDRAM */
 377 #endif /* CFG_LSDRAM */
 378
 379 #define CONFIG_CLOCKS_IN_MHZ    1      /* clocks passsed to Linux in MHz */
 380
 381 #define CFG_LOAD_ADDR     0x00100000   /* default load address */
 382 #define CFG_TFTP_LOADADDR 0x00100000   /* default load address for network file downloads */
 383
 384 #define CFG_HZ            1000         /* decrementer freq: 1 ms ticks */
 385
 386 /* valid baudrates */
 387 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 388
 389 /*
 390  * Low Level Configuration Settings
 391  * (address mappings, register initial values, etc.)
 392  * You should know what you are doing if you make changes here.
 393  */
 394
 395 #define CFG_FLASH_BASE    CFG_FLASH0_BASE
 396 #define CFG_SDRAM_BASE    CFG_SDRAM0_BASE
 397
 398 /*-----------------------------------------------------------------------
 399  * Hard Reset Configuration Words
 400  */
 401
 402 #if defined(CFG_SBC_BOOT_LOW)
 403 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (HRCW_CIP | HRCW_BMS)
 404 #else
 405 #  define  CFG_SBC_HRCW_BOOT_FLAGS  (0x00000000)
 406 #endif /* defined(CFG_SBC_BOOT_LOW) */
 407
 408 #ifdef CFG_EP8260_H2
 409 /* get the HRCW ISB field from CFG_DEFAULT_IMMR */
 410 #define CFG_SBC_HRCW_IMMR ( ((CFG_DEFAULT_IMMR & 0x10000000) >> 10) |\
 411                             ((CFG_DEFAULT_IMMR & 0x01000000) >> 7)  |\
 412                             ((CFG_DEFAULT_IMMR & 0x00100000) >> 4) )
 413
 414 #define CFG_HRCW_MASTER (HRCW_EBM                |\
 415                          HRCW_L2CPC01            |\
 416                          CFG_SBC_HRCW_IMMR       |\
 417                          HRCW_APPC10             |\
 418                          HRCW_CS10PC01           |\
 419                          CFG_SBC_MODCK_H         |\
 420                          CFG_SBC_HRCW_BOOT_FLAGS)
 421 #else
 422 #define CFG_HRCW_MASTER 0x10400245
 423 #endif
 424
 425 /* no slaves */
 426 #define CFG_HRCW_SLAVE1 0
 427 #define CFG_HRCW_SLAVE2 0
 428 #define CFG_HRCW_SLAVE3 0
 429 #define CFG_HRCW_SLAVE4 0
 430 #define CFG_HRCW_SLAVE5 0
 431 #define CFG_HRCW_SLAVE6 0
 432 #define CFG_HRCW_SLAVE7 0
 433
 434 /*-----------------------------------------------------------------------
 435  * Definitions for initial stack pointer and data area (in DPRAM)
 436  */
 437 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 438 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 439 #define CFG_GBL_DATA_SIZE      128     /* bytes reserved for initial data */
 440 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 441 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 442
 443 /*-----------------------------------------------------------------------
 444  * Start addresses for the final memory configuration
 445  * (Set up by the startup code)
 446  * Please note that CFG_SDRAM_BASE _must_ start at 0
 447  * Note also that the logic that sets CFG_RAMBOOT is platform dependent.
 448  */
 449 #define CFG_MONITOR_BASE          TEXT_BASE
 450
 451
 452 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 453 #  define CFG_RAMBOOT
 454 #endif
 455
 456 #define CFG_MONITOR_LEN      (256 << 10)     /* Reserve 256 kB for Monitor   */
 457 #define CFG_MALLOC_LEN       (128 << 10)     /* Reserve 128 kB for malloc()  */
 458
 459 /*
 460  * For booting Linux, the board info and command line data
 461  * have to be in the first 8 MB of memory, since this is
 462  * the maximum mapped by the Linux kernel during initialization.
 463  */
 464 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 465
 466 /*-----------------------------------------------------------------------
 467  * FLASH and environment organization
 468  */
 469 #define CFG_MAX_FLASH_BANKS   1       /* max number of memory banks         */
 470 #ifdef CFG_EP8260_H2
 471 #define CFG_MAX_FLASH_SECT    128      /* max number of sectors on one chip  */
 472 #else
 473 #define CFG_MAX_FLASH_SECT    71      /* max number of sectors on one chip  */
 474 #endif
 475
 476 #ifdef CFG_EP8260_H2
 477 #define CFG_FLASH_ERASE_TOUT  240000  /* Timeout for Flash Erase (in ms)    */
 478 #define CFG_FLASH_WRITE_TOUT  500     /* Timeout for Flash Write (in ms)    */
 479 #else
 480 #define CFG_FLASH_ERASE_TOUT  8000    /* Timeout for Flash Erase (in ms)    */
 481 #define CFG_FLASH_WRITE_TOUT  1       /* Timeout for Flash Write (in ms)    */
 482 #endif
 483
 484 #ifndef CFG_RAMBOOT
 485 #  define CFG_ENV_IS_IN_FLASH  1
 486
 487 #  ifdef CFG_ENV_IN_OWN_SECT
 488 #    define CFG_ENV_ADDR       (CFG_MONITOR_BASE + 0x40000)
 489 #    define CFG_ENV_SECT_SIZE  0x40000
 490 #  else
 491 #    define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_ENV_SECT_SIZE)
 492 #    define CFG_ENV_SIZE       0x1000  /* Total Size of Environment Sector */
 493 #    define CFG_ENV_SECT_SIZE  0x10000 /* see README - env sect real size */
 494 #  endif /* CFG_ENV_IN_OWN_SECT */
 495 #else
 496 #  define CFG_ENV_IS_IN_NVRAM  1
 497 #  define CFG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
 498 #  define CFG_ENV_SIZE         0x200
 499 #endif /* CFG_RAMBOOT */
 500
 501 /*-----------------------------------------------------------------------
 502  * Cache Configuration
 503  */
 504 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU */
 505
 506 #if defined(CONFIG_CMD_KGDB)
 507 #  define CFG_CACHELINE_SHIFT     5     /* log base 2 of the above value */
 508 #endif
 509
 510 /*-----------------------------------------------------------------------
 511  * HIDx - Hardware Implementation-dependent Registers                    2-11
 512  *-----------------------------------------------------------------------
 513  * HID0 also contains cache control - initially enable both caches and
 514  * invalidate contents, then the final state leaves only the instruction
 515  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 516  * but Soft reset does not.
 517  *
 518  * HID1 has only read-only information - nothing to set.
 519  */
 520 #define CFG_HID0_INIT   (HID0_ICE  |\
 521                          HID0_DCE  |\
 522                          HID0_ICFI |\
 523                          HID0_DCI  |\
 524                          HID0_IFEM |\
 525                          HID0_ABE)
 526 #ifdef CFG_LSDRAM
 527 /* 8260 local bus is NOT cacheable */
 528 #define CFG_HID0_FINAL  (/*HID0_ICE  |*/\
 529                          HID0_IFEM |\
 530                          HID0_ABE  |\
 531                          HID0_EMCP)
 532 #else /* !CFG_LSDRAM */
 533 #define CFG_HID0_FINAL  (HID0_ICE  |\
 534                          HID0_IFEM |\
 535                          HID0_ABE  |\
 536                          HID0_EMCP)
 537 #endif /* CFG_LSDRAM */
 538
 539 #define CFG_HID2        0
 540
 541 /*-----------------------------------------------------------------------
 542  * RMR - Reset Mode Register
 543  *-----------------------------------------------------------------------
 544  */
 545 #define CFG_RMR         0
 546
 547 /*-----------------------------------------------------------------------
 548  * BCR - Bus Configuration                                       4-25
 549  *-----------------------------------------------------------------------
 550  */
 551 #define CFG_BCR         (BCR_EBM   |\
 552                          BCR_PLDP  |\
 553                          BCR_EAV   |\
 554                          BCR_NPQM0)
 555
 556 /*-----------------------------------------------------------------------
 557  * SIUMCR - SIU Module Configuration                             4-31
 558  *-----------------------------------------------------------------------
 559  */
 560 #define CFG_SIUMCR      (SIUMCR_L2CPC01 |\
 561                          SIUMCR_APPC10  |\
 562                          SIUMCR_CS10PC01)
 563
 564 /*-----------------------------------------------------------------------
 565  * SYPCR - System Protection Control                            11-9
 566  * SYPCR can only be written once after reset!
 567  *-----------------------------------------------------------------------
 568  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 569  */
 570 #ifdef CFG_EP8260_H2
 571 /* TBD: Find out why setting the BMT to 0xff causes the FCC to
 572  * generate TX buffer underrun errors for large packets under
 573  * Linux
 574  */
 575 #define CFG_SYPCR_BMT   0x00000600
 576 #else
 577 #define CFG_SYPCR_BMT   SYPCR_BMT
 578 #endif
 579
 580 #ifdef CFG_LSDRAM
 581 #define CFG_SYPCR       (SYPCR_SWTC |\
 582                          CFG_SYPCR_BMT  |\
 583                          SYPCR_PBME |\
 584                          SYPCR_LBME |\
 585                          SYPCR_SWP)
 586 #else
 587 #define CFG_SYPCR       (SYPCR_SWTC |\
 588                          CFG_SYPCR_BMT  |\
 589                          SYPCR_PBME |\
 590                          SYPCR_SWP)
 591 #endif
 592
 593 /*-----------------------------------------------------------------------
 594  * TMCNTSC - Time Counter Status and Control                     4-40
 595  *-----------------------------------------------------------------------
 596  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 597  * and enable Time Counter
 598  */
 599 #define CFG_TMCNTSC     (TMCNTSC_SEC |\
 600                          TMCNTSC_ALR |\
 601                          TMCNTSC_TCF |\
 602                          TMCNTSC_TCE)
 603
 604 /*-----------------------------------------------------------------------
 605  * PISCR - Periodic Interrupt Status and Control                 4-42
 606  *-----------------------------------------------------------------------
 607  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 608  * Periodic timer
 609  */
 610 #ifdef CFG_EP8260_H2
 611 #define CFG_PISCR       (PISCR_PS  |\
 612                          PISCR_PTF |\
 613                          PISCR_PTE)
 614 #else
 615 #define CFG_PISCR       0
 616 #endif
 617
 618 /*-----------------------------------------------------------------------
 619  * SCCR - System Clock Control                                   9-8
 620  *-----------------------------------------------------------------------
 621  */
 622 #ifdef CFG_EP8260_H2
 623 #define CFG_SCCR        (SCCR_DFBRG00)
 624 #else
 625 #define CFG_SCCR        (SCCR_DFBRG01)
 626 #endif
 627
 628 /*-----------------------------------------------------------------------
 629  * RCCR - RISC Controller Configuration                         13-7
 630  *-----------------------------------------------------------------------
 631  */
 632 #define CFG_RCCR        0
 633
 634 /*-----------------------------------------------------------------------
 635  * MPTPR - Memory Refresh Timer Prescale Register               10-32
 636  *-----------------------------------------------------------------------
 637  */
 638 #define CFG_MPTPR       (0x0A00 & MPTPR_PTP_MSK)
 639
 640 /*
 641  * Init Memory Controller:
 642  *
 643  * Bank Bus     Machine PortSz  Device
 644  * ---- ---     ------- ------  ------
 645  *  0   60x     GPCM    64 bit  FLASH (BGA - 16MB AMD AM29DL323DB90WDI)
 646  *  1   60x     SDRAM   64 bit  SDRAM (BGA - 64MB Micron 48LC8M16A2TG)
 647  *  2   Local   SDRAM   32 bit  SDRAM (BGA - 32MB Micron 48LC8M16A2TG)
 648  *  3   unused
 649  *  4   60x     GPCM     8 bit  Board Regs, NVRTC
 650  *  5   unused
 651  *  6   unused
 652  *  7   unused
 653  *  8   PCMCIA
 654  *  9   unused
 655  * 10   unused
 656  * 11   unused
 657 */
 658
 659 /*-----------------------------------------------------------------------
 660  * BRx - Base Register
 661  *     Ref: Section 10.3.1 on page 10-14
 662  * ORx - Option Register
 663  *     Ref: Section 10.3.2 on page 10-18
 664  *-----------------------------------------------------------------------
 665  */
 666
 667 /* Bank 0 - FLASH
 668  *
 669  */
 670 #define CFG_BR0_PRELIM  ((CFG_FLASH0_BASE & BRx_BA_MSK) |\
 671                          BRx_PS_64                      |\
 672                          BRx_DECC_NONE                  |\
 673                          BRx_MS_GPCM_P                  |\
 674                          BRx_V)
 675
 676 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH0_SIZE)     |\
 677                          ORxG_CSNT                      |\
 678                          ORxG_ACS_DIV1                  |\
 679                          ORxG_SCY_8_CLK                 |\
 680                          ORxG_EHTR)
 681
 682 /* Bank 1 - SDRAM
 683  * PSDRAM
 684  */
 685 #define CFG_BR1_PRELIM  ((CFG_SDRAM0_BASE & BRx_BA_MSK) |\
 686                          BRx_PS_64                      |\
 687                          BRx_MS_SDRAM_P                 |\
 688                          BRx_V)
 689
 690 #define CFG_OR1_PRELIM  (MEG_TO_AM(CFG_SDRAM0_SIZE)     |\
 691                          ORxS_BPD_4                     |\
 692                          ORxS_ROWST_PBI1_A6             |\
 693                          ORxS_NUMR_12)
 694
 695 #ifdef CFG_EP8260_H2
 696 #define CFG_PSDMR       0xC34E246E
 697 #else
 698 #define CFG_PSDMR       0xC34E2462
 699 #endif
 700
 701 #define CFG_PSRT        0x64
 702
 703 #ifdef CFG_LSDRAM
 704 /* Bank 2 - SDRAM
 705  * LSDRAM
 706  */
 707
 708   #define CFG_BR2_PRELIM  ((CFG_SDRAM1_BASE & BRx_BA_MSK) |\
 709                            BRx_PS_32                      |\
 710                            BRx_MS_SDRAM_L                 |\
 711                            BRx_V)
 712
 713   #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM1_SIZE)     |\
 714                            ORxS_BPD_4                     |\
 715                            ORxS_ROWST_PBI0_A9             |\
 716                            ORxS_NUMR_12)
 717
 718   #define CFG_LSDMR      0x416A2562
 719   #define CFG_LSRT      0x64
 720 #else
 721   #define CFG_LSRT      0x0
 722 #endif /* CFG_LSDRAM */
 723
 724 /* Bank 4 - On board registers
 725  * NVRTC and BCSR
 726  */
 727 #define CFG_BR4_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
 728                            BRx_PS_8                     |\
 729                            BRx_MS_GPCM_P                |\
 730                            BRx_V)
 731 /*
 732 #define CFG_OR4_PRELIM    (ORxG_AM_MSK                 |\
 733                            ORxG_CSNT                   |\
 734                            ORxG_ACS_DIV1               |\
 735                            ORxG_SCY_10_CLK              |\
 736                            ORxG_TRLX)
 737 */
 738 #define CFG_OR4_PRELIM 0xfff00854
 739
 740 #ifdef _NOT_USED_SINCE_NOT_WORKING_
 741 /* Bank 8 - On board registers
 742  * PCMCIA (currently not working!)
 743  */
 744 #define CFG_BR8_PRELIM   ((CFG_REGS_BASE & BRx_BA_MSK)  |\
 745                            BRx_PS_16                     |\
 746                            BRx_MS_GPCM_P                |\
 747                            BRx_V)
 748
 749 #define CFG_OR8_PRELIM    (ORxG_AM_MSK                 |\
 750                            ORxG_CSNT                   |\
 751                            ORxG_ACS_DIV1               |\
 752                            ORxG_SETA                   |\
 753                            ORxG_SCY_10_CLK)
 754 #endif
 755
 756 /*
 757  * Internal Definitions
 758  *
 759  * Boot Flags
 760  */
 761 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH  */
 762 #define BOOTFLAG_WARM   0x02    /* Software reboot                   */
 763
 764 /*
 765  * JFFS2 partitions
 766  *
 767  */
 768 /* No command line, one static partition, whole device */
 769 #undef CONFIG_JFFS2_CMDLINE
 770 #define CONFIG_JFFS2_DEV                "nor0"
 771 #define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 772 #define CONFIG_JFFS2_PART_OFFSET        0x00000000
 773
 774 /* mtdparts command line support */
 775 /* Note: fake mtd_id used, no linux mtd map file */
 776 /*
 777 #define CONFIG_JFFS2_CMDLINE
 778 #define MTDIDS_DEFAULT          ""
 779 #define MTDPARTS_DEFAULT        ""
 780 */
 781
 782 #endif  /* __CONFIG_H */