include/configs/lager.h

   1 /*
   2  * include/configs/lager.h
   3  *     This file is lager board configuration.
   4  *
   5  * Copyright (C) 2013, 2014 Renesas Electronics Corporation
   6  *
   7  * SPDX-License-Identifier: GPL-2.0
   8  */
   9
  10 #ifndef __LAGER_H
  11 #define __LAGER_H
  12
  13 #undef DEBUG
  14 #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Lager"
  15
  16 #include "rcar-gen2-common.h"
  17
  18 #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
  19 #define CONFIG_SYS_TEXT_BASE    0xB0000000
  20 #else
  21 #define CONFIG_SYS_TEXT_BASE    0xE8080000
  22 #endif
  23
  24 /* STACK */
  25 #if defined(CONFIGF_RMOBILE_EXTRAM_BOOT)
  26 #define CONFIG_SYS_INIT_SP_ADDR         0xB003FFFC
  27 #else
  28 #define CONFIG_SYS_INIT_SP_ADDR         0xE827FFFC
  29 #endif
  30 #define STACK_AREA_SIZE                 0xC000
  31 #define LOW_LEVEL_MERAM_STACK   \
  32                 (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
  33
  34 /* MEMORY */
  35 #define RCAR_GEN2_SDRAM_BASE            0x40000000
  36 #define RCAR_GEN2_SDRAM_SIZE            (2048u * 1024 * 1024)
  37 #define RCAR_GEN2_UBOOT_SDRAM_SIZE      (512 * 1024 * 1024)
  38
  39 /* SCIF */
  40
  41 /* SPI */
  42 #define CONFIG_SPI
  43 #define CONFIG_SH_QSPI
  44
  45 /* SH Ether */
  46 #define CONFIG_SH_ETHER_USE_PORT        0
  47 #define CONFIG_SH_ETHER_PHY_ADDR        0x1
  48 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
  49 #define CONFIG_SH_ETHER_ALIGNE_SIZE     64
  50 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
  51 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
  52 #define CONFIG_BITBANGMII
  53 #define CONFIG_BITBANGMII_MULTI
  54
  55 /* I2C */
  56 #define CONFIG_SYS_I2C
  57 #define CONFIG_SYS_I2C_RCAR
  58 #define CONFIG_SYS_RCAR_I2C0_SPEED      400000
  59 #define CONFIG_SYS_RCAR_I2C1_SPEED      400000
  60 #define CONFIG_SYS_RCAR_I2C2_SPEED      400000
  61 #define CONFIG_SYS_RCAR_I2C3_SPEED      400000
  62 #define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS     4
  63
  64 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
  65
  66 /* Board Clock */
  67 #define RMOBILE_XTAL_CLK        20000000u
  68 #define CONFIG_SYS_CLK_FREQ     RMOBILE_XTAL_CLK
  69 #define CONFIG_SH_TMU_CLK_FREQ  (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
  70 #define CONFIG_PLL1_CLK_FREQ    (CONFIG_SYS_CLK_FREQ * 156 / 2)
  71 #define CONFIG_PLL1_DIV2_CLK_FREQ       (CONFIG_PLL1_CLK_FREQ / 2)
  72 #define CONFIG_MP_CLK_FREQ      (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
  73 #define CONFIG_HP_CLK_FREQ      (CONFIG_PLL1_CLK_FREQ / 12)
  74
  75 #define CONFIG_SYS_TMU_CLK_DIV  4
  76
  77 /* USB */
  78 #define CONFIG_USB_EHCI_RMOBILE
  79 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
  80
  81 /* MMC */
  82 #define CONFIG_SH_MMCIF
  83 #define CONFIG_SH_MMCIF_ADDR            0xEE220000
  84 #define CONFIG_SH_MMCIF_CLK             97500000
  85
  86 /* Module stop status bits */
  87 /* INTC-RT */
  88 #define CONFIG_SMSTP0_ENA       0x00400000
  89 /* MSIF */
  90 #define CONFIG_SMSTP2_ENA       0x00002000
  91 /* INTC-SYS, IRQC */
  92 #define CONFIG_SMSTP4_ENA       0x00000180
  93 /* SCIF0 */
  94 #define CONFIG_SMSTP7_ENA       0x00200000
  95
  96 /* SDHI */
  97 #define CONFIG_SH_SDHI_FREQ     97500000
  98
  99 #endif  /* __LAGER_H */