include/configs/ls1043aqds.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1043AQDS_H__
   8 #define __LS1043AQDS_H__
   9
  10 #include "ls1043a_common.h"
  11
  12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
  13 #define CONFIG_SYS_TEXT_BASE            0x82000000
  14 #elif defined(CONFIG_QSPI_BOOT)
  15 #define CONFIG_SYS_TEXT_BASE            0x40010000
  16 #else
  17 #define CONFIG_SYS_TEXT_BASE            0x60100000
  18 #endif
  19
  20 #ifndef __ASSEMBLY__
  21 unsigned long get_board_sys_clk(void);
  22 unsigned long get_board_ddr_clk(void);
  23 #endif
  24
  25 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  26 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  27
  28 #define CONFIG_SKIP_LOWLEVEL_INIT
  29
  30 #define CONFIG_LAYERSCAPE_NS_ACCESS
  31
  32 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  33 /* Physical Memory Map */
  34 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  35 #define CONFIG_NR_DRAM_BANKS            2
  36
  37 #define CONFIG_DDR_SPD
  38 #define SPD_EEPROM_ADDRESS              0x51
  39 #define CONFIG_SYS_SPD_BUS_NUM          0
  40
  41 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  42
  43 #define CONFIG_DDR_ECC
  44 #ifdef CONFIG_DDR_ECC
  45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  46 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  47 #endif
  48
  49 #ifdef CONFIG_SYS_DPAA_FMAN
  50 #define CONFIG_FMAN_ENET
  51 #define CONFIG_PHYLIB
  52 #define CONFIG_PHY_VITESSE
  53 #define CONFIG_PHY_REALTEK
  54 #define CONFIG_PHYLIB_10G
  55 #define RGMII_PHY1_ADDR         0x1
  56 #define RGMII_PHY2_ADDR         0x2
  57 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  58 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  59 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  60 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  61 /* PHY address on QSGMII riser card on slot 1 */
  62 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
  63 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
  64 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
  65 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
  66 /* PHY address on QSGMII riser card on slot 2 */
  67 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  68 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  69 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  70 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  71 #endif
  72
  73 #ifdef CONFIG_RAMBOOT_PBL
  74 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
  75 #endif
  76
  77 #ifdef CONFIG_NAND_BOOT
  78 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
  79 #endif
  80
  81 #ifdef CONFIG_SD_BOOT
  82 #ifdef CONFIG_SD_BOOT_QSPI
  83 #define CONFIG_SYS_FSL_PBL_RCW \
  84         board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
  85 #else
  86 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
  87 #endif
  88 #endif
  89
  90 /* LPUART */
  91 #ifdef CONFIG_LPUART
  92 #define CONFIG_LPUART_32B_REG
  93 #endif
  94
  95 /* SATA */
  96 #define CONFIG_LIBATA
  97 #define CONFIG_SCSI_AHCI
  98 #define CONFIG_SCSI_AHCI_PLAT
  99 #define CONFIG_SCSI
 100
 101 #define CONFIG_PARTITION_UUIDS
 102 #define CONFIG_CMD_GPT
 103
 104 /* EEPROM */
 105 #define CONFIG_ID_EEPROM
 106 #define CONFIG_SYS_I2C_EEPROM_NXID
 107 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 108 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 109 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 110 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 111 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 112
 113 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
 114
 115 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
 116 #define CONFIG_SYS_SCSI_MAX_LUN                 1
 117 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 118                                                 CONFIG_SYS_SCSI_MAX_LUN)
 119
 120 /*
 121  * IFC Definitions
 122  */
 123 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 124 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 125 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 126                                 CSPR_PORT_SIZE_16 | \
 127                                 CSPR_MSEL_NOR | \
 128                                 CSPR_V)
 129 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 130 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 131                                 + 0x8000000) | \
 132                                 CSPR_PORT_SIZE_16 | \
 133                                 CSPR_MSEL_NOR | \
 134                                 CSPR_V)
 135 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 136
 137 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 138                                         CSOR_NOR_TRHZ_80)
 139 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 140                                         FTIM0_NOR_TEADC(0x5) | \
 141                                         FTIM0_NOR_TEAHC(0x5))
 142 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 143                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 144                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 145 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 146                                         FTIM2_NOR_TCH(0x4) | \
 147                                         FTIM2_NOR_TWPH(0xe) | \
 148                                         FTIM2_NOR_TWP(0x1c))
 149 #define CONFIG_SYS_NOR_FTIM3            0
 150
 151 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 152 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 153 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 154 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 155
 156 #define CONFIG_SYS_FLASH_EMPTY_INFO
 157 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 158                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 159
 160 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 161 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 162
 163 /*
 164  * NAND Flash Definitions
 165  */
 166 #define CONFIG_NAND_FSL_IFC
 167
 168 #define CONFIG_SYS_NAND_BASE            0x7e800000
 169 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 170
 171 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 172
 173 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 174                                 | CSPR_PORT_SIZE_8      \
 175                                 | CSPR_MSEL_NAND        \
 176                                 | CSPR_V)
 177 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 178 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 179                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 180                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 181                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 182                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 183                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 184                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 185
 186 #define CONFIG_SYS_NAND_ONFI_DETECTION
 187
 188 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 189                                         FTIM0_NAND_TWP(0x18)   | \
 190                                         FTIM0_NAND_TWCHT(0x7) | \
 191                                         FTIM0_NAND_TWH(0xa))
 192 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 193                                         FTIM1_NAND_TWBE(0x39)  | \
 194                                         FTIM1_NAND_TRR(0xe)   | \
 195                                         FTIM1_NAND_TRP(0x18))
 196 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 197                                         FTIM2_NAND_TREH(0xa) | \
 198                                         FTIM2_NAND_TWHRE(0x1e))
 199 #define CONFIG_SYS_NAND_FTIM3           0x0
 200
 201 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 202 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 203 #define CONFIG_MTD_NAND_VERIFY_WRITE
 204 #define CONFIG_CMD_NAND
 205
 206 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 207 #endif
 208
 209 #ifdef CONFIG_NAND_BOOT
 210 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 211 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 212 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 << 10)
 213 #endif
 214
 215 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 216 #define CONFIG_QIXIS_I2C_ACCESS
 217 #define CONFIG_SYS_I2C_EARLY_INIT
 218 #define CONFIG_SYS_NO_FLASH
 219 #endif
 220
 221 /*
 222  * QIXIS Definitions
 223  */
 224 #define CONFIG_FSL_QIXIS
 225
 226 #ifdef CONFIG_FSL_QIXIS
 227 #define QIXIS_BASE                      0x7fb00000
 228 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 229 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 230 #define QIXIS_LBMAP_SWITCH              6
 231 #define QIXIS_LBMAP_MASK                0x0f
 232 #define QIXIS_LBMAP_SHIFT               0
 233 #define QIXIS_LBMAP_DFLTBANK            0x00
 234 #define QIXIS_LBMAP_ALTBANK             0x04
 235 #define QIXIS_LBMAP_NAND                0x09
 236 #define QIXIS_LBMAP_SD                  0x00
 237 #define QIXIS_LBMAP_SD_QSPI             0xff
 238 #define QIXIS_LBMAP_QSPI                0xff
 239 #define QIXIS_RCW_SRC_NAND              0x106
 240 #define QIXIS_RCW_SRC_SD                0x040
 241 #define QIXIS_RCW_SRC_QSPI              0x045
 242 #define QIXIS_RST_CTL_RESET             0x41
 243 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 244 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 245 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 246
 247 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 248 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 249                                         CSPR_PORT_SIZE_8 | \
 250                                         CSPR_MSEL_GPCM | \
 251                                         CSPR_V)
 252 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 253 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 254                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 255                                         CSOR_NOR_TRHZ_80)
 256
 257 /*
 258  * QIXIS Timing parameters for IFC GPCM
 259  */
 260 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 261                                         FTIM0_GPCM_TEADC(0x20) | \
 262                                         FTIM0_GPCM_TEAHC(0x10))
 263 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 264                                         FTIM1_GPCM_TRAD(0x1f))
 265 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 266                                         FTIM2_GPCM_TCH(0x8) | \
 267                                         FTIM2_GPCM_TWP(0xf0))
 268 #define CONFIG_SYS_FPGA_FTIM3           0x0
 269 #endif
 270
 271 #ifdef CONFIG_NAND_BOOT
 272 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 273 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 274 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 275 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 276 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 277 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 278 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 279 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 280 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 281 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 282 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 283 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 284 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 285 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 286 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 287 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 288 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 289 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 290 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 291 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 292 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 293 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 294 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 295 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 296 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 297 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 298 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 299 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 300 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 301 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 302 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 303 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 304 #else
 305 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 306 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 307 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 308 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 309 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 310 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 311 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 312 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 313 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 314 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 315 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 316 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 317 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 318 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 319 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 320 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 321 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 322 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 323 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 324 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 325 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 326 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 327 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 328 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 329 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 330 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 331 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 332 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 333 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 334 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 335 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 336 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 337 #endif
 338
 339 /*
 340  * I2C bus multiplexer
 341  */
 342 #define I2C_MUX_PCA_ADDR_PRI            0x77
 343 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 344 #define I2C_RETIMER_ADDR                0x18
 345 #define I2C_MUX_CH_DEFAULT              0x8
 346 #define I2C_MUX_CH_CH7301               0xC
 347 #define I2C_MUX_CH5                     0xD
 348 #define I2C_MUX_CH7                     0xF
 349
 350 #define I2C_MUX_CH_VOL_MONITOR 0xa
 351
 352 /* Voltage monitor on channel 2*/
 353 #define I2C_VOL_MONITOR_ADDR           0x40
 354 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 355 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 356 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 357
 358 #define CONFIG_VID_FLS_ENV              "ls1043aqds_vdd_mv"
 359 #ifndef CONFIG_SPL_BUILD
 360 #define CONFIG_VID
 361 #endif
 362 #define CONFIG_VOL_MONITOR_IR36021_SET
 363 #define CONFIG_VOL_MONITOR_INA220
 364 /* The lowest and highest voltage allowed for LS1043AQDS */
 365 #define VDD_MV_MIN                      819
 366 #define VDD_MV_MAX                      1212
 367
 368 /* QSPI device */
 369 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 370 #define CONFIG_FSL_QSPI
 371 #ifdef CONFIG_FSL_QSPI
 372 #define CONFIG_SPI_FLASH_SPANSION
 373 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 374 #define FSL_QSPI_FLASH_NUM              2
 375 #endif
 376 #endif
 377
 378 /* USB */
 379 #define CONFIG_HAS_FSL_XHCI_USB
 380 #ifdef CONFIG_HAS_FSL_XHCI_USB
 381 #define CONFIG_USB_XHCI_FSL
 382 #define CONFIG_USB_MAX_CONTROLLER_COUNT         3
 383 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 384 #endif
 385
 386 /*
 387  * Miscellaneous configurable options
 388  */
 389 #define CONFIG_MISC_INIT_R
 390 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 391 #define CONFIG_AUTO_COMPLETE
 392 #define CONFIG_SYS_PBSIZE               \
 393                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 394 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 395
 396 #define CONFIG_SYS_MEMTEST_START        0x80000000
 397 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 398
 399 #define CONFIG_SYS_HZ                   1000
 400
 401 /*
 402  * Stack sizes
 403  * The stack sizes are set up in start.S using the settings below
 404  */
 405 #define CONFIG_STACKSIZE                (30 * 1024)
 406
 407 #define CONFIG_SYS_INIT_SP_OFFSET \
 408         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 409
 410 #ifdef CONFIG_SPL_BUILD
 411 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 412 #else
 413 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 414 #endif
 415
 416 /*
 417  * Environment
 418  */
 419 #define CONFIG_ENV_OVERWRITE
 420
 421 #ifdef CONFIG_NAND_BOOT
 422 #define CONFIG_ENV_IS_IN_NAND
 423 #define CONFIG_ENV_SIZE                 0x2000
 424 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 425 #elif defined(CONFIG_SD_BOOT)
 426 #define CONFIG_ENV_OFFSET               (1024 * 1024)
 427 #define CONFIG_ENV_IS_IN_MMC
 428 #define CONFIG_SYS_MMC_ENV_DEV          0
 429 #define CONFIG_ENV_SIZE                 0x2000
 430 #elif defined(CONFIG_QSPI_BOOT)
 431 #define CONFIG_ENV_IS_IN_SPI_FLASH
 432 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 433 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 434 #define CONFIG_ENV_SECT_SIZE            0x10000
 435 #else
 436 #define CONFIG_ENV_IS_IN_FLASH
 437 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 438 #define CONFIG_ENV_SECT_SIZE            0x20000
 439 #define CONFIG_ENV_SIZE                 0x20000
 440 #endif
 441
 442 #define CONFIG_CMDLINE_TAG
 443
 444 #include <asm/fsl_secure_boot.h>
 445
 446 #endif /* __LS1043AQDS_H__ */