include/configs/ls1043aqds.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS1043AQDS_H__
   8 #define __LS1043AQDS_H__
   9
  10 #include "ls1043a_common.h"
  11
  12 #define CONFIG_DISPLAY_CPUINFO
  13 #define CONFIG_DISPLAY_BOARDINFO
  14
  15 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
  16 #define CONFIG_SYS_TEXT_BASE            0x82000000
  17 #elif defined(CONFIG_QSPI_BOOT)
  18 #define CONFIG_SYS_TEXT_BASE            0x40010000
  19 #else
  20 #define CONFIG_SYS_TEXT_BASE            0x60100000
  21 #endif
  22
  23 #ifndef __ASSEMBLY__
  24 unsigned long get_board_sys_clk(void);
  25 unsigned long get_board_ddr_clk(void);
  26 #endif
  27
  28 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  29 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  30
  31 #define CONFIG_SKIP_LOWLEVEL_INIT
  32
  33 #define CONFIG_LAYERSCAPE_NS_ACCESS
  34
  35 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  36 /* Physical Memory Map */
  37 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  38 #define CONFIG_NR_DRAM_BANKS            2
  39
  40 #define CONFIG_DDR_SPD
  41 #define SPD_EEPROM_ADDRESS              0x51
  42 #define CONFIG_SYS_SPD_BUS_NUM          0
  43
  44 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  45 #ifndef CONFIG_SYS_FSL_DDR4
  46 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
  47 #endif
  48
  49 #define CONFIG_DDR_ECC
  50 #ifdef CONFIG_DDR_ECC
  51 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  52 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  53 #endif
  54
  55 #ifdef CONFIG_SYS_DPAA_FMAN
  56 #define CONFIG_FMAN_ENET
  57 #define CONFIG_PHYLIB
  58 #define CONFIG_PHY_VITESSE
  59 #define CONFIG_PHY_REALTEK
  60 #define CONFIG_PHYLIB_10G
  61 #define RGMII_PHY1_ADDR         0x1
  62 #define RGMII_PHY2_ADDR         0x2
  63 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
  64 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
  65 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
  66 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
  67 /* PHY address on QSGMII riser card on slot 1 */
  68 #define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4
  69 #define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5
  70 #define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6
  71 #define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7
  72 /* PHY address on QSGMII riser card on slot 2 */
  73 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
  74 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
  75 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
  76 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
  77 #endif
  78
  79 #ifdef CONFIG_RAMBOOT_PBL
  80 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg
  81 #endif
  82
  83 #ifdef CONFIG_NAND_BOOT
  84 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg
  85 #endif
  86
  87 #ifdef CONFIG_SD_BOOT
  88 #ifdef CONFIG_SD_BOOT_QSPI
  89 #define CONFIG_SYS_FSL_PBL_RCW \
  90         board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg
  91 #else
  92 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg
  93 #endif
  94 #endif
  95
  96 /* LPUART */
  97 #ifdef CONFIG_LPUART
  98 #define CONFIG_LPUART_32B_REG
  99 #endif
 100
 101 /* SATA */
 102 #define CONFIG_LIBATA
 103 #define CONFIG_SCSI_AHCI
 104 #define CONFIG_SCSI_AHCI_PLAT
 105 #define CONFIG_SCSI
 106 #define CONFIG_DOS_PARTITION
 107 #define CONFIG_BOARD_LATE_INIT
 108
 109 /* EEPROM */
 110 #define CONFIG_ID_EEPROM
 111 #define CONFIG_SYS_I2C_EEPROM_NXID
 112 #define CONFIG_SYS_EEPROM_BUS_NUM               0
 113 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x57
 114 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 115 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 116 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 117
 118 #define CONFIG_SYS_SATA                         AHCI_BASE_ADDR
 119
 120 #define CONFIG_SYS_SCSI_MAX_SCSI_ID             1
 121 #define CONFIG_SYS_SCSI_MAX_LUN                 1
 122 #define CONFIG_SYS_SCSI_MAX_DEVICE              (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 123                                                 CONFIG_SYS_SCSI_MAX_LUN)
 124
 125 /*
 126  * IFC Definitions
 127  */
 128 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 129 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 130 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 131                                 CSPR_PORT_SIZE_16 | \
 132                                 CSPR_MSEL_NOR | \
 133                                 CSPR_V)
 134 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 135 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 136                                 + 0x8000000) | \
 137                                 CSPR_PORT_SIZE_16 | \
 138                                 CSPR_MSEL_NOR | \
 139                                 CSPR_V)
 140 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 141
 142 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 143                                         CSOR_NOR_TRHZ_80)
 144 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 145                                         FTIM0_NOR_TEADC(0x5) | \
 146                                         FTIM0_NOR_TEAHC(0x5))
 147 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 148                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 149                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 150 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 151                                         FTIM2_NOR_TCH(0x4) | \
 152                                         FTIM2_NOR_TWPH(0xe) | \
 153                                         FTIM2_NOR_TWP(0x1c))
 154 #define CONFIG_SYS_NOR_FTIM3            0
 155
 156 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 157 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 158 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 159 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 160
 161 #define CONFIG_SYS_FLASH_EMPTY_INFO
 162 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 163                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 164
 165 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 166 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 167
 168 /*
 169  * NAND Flash Definitions
 170  */
 171 #define CONFIG_NAND_FSL_IFC
 172
 173 #define CONFIG_SYS_NAND_BASE            0x7e800000
 174 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 175
 176 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 177
 178 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 179                                 | CSPR_PORT_SIZE_8      \
 180                                 | CSPR_MSEL_NAND        \
 181                                 | CSPR_V)
 182 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 183 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 184                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 185                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 186                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 187                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 188                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 189                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 190
 191 #define CONFIG_SYS_NAND_ONFI_DETECTION
 192
 193 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 194                                         FTIM0_NAND_TWP(0x18)   | \
 195                                         FTIM0_NAND_TWCHT(0x7) | \
 196                                         FTIM0_NAND_TWH(0xa))
 197 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 198                                         FTIM1_NAND_TWBE(0x39)  | \
 199                                         FTIM1_NAND_TRR(0xe)   | \
 200                                         FTIM1_NAND_TRP(0x18))
 201 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 202                                         FTIM2_NAND_TREH(0xa) | \
 203                                         FTIM2_NAND_TWHRE(0x1e))
 204 #define CONFIG_SYS_NAND_FTIM3           0x0
 205
 206 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 207 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 208 #define CONFIG_MTD_NAND_VERIFY_WRITE
 209 #define CONFIG_CMD_NAND
 210
 211 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 212 #endif
 213
 214 #ifdef CONFIG_NAND_BOOT
 215 #define CONFIG_SPL_PAD_TO               0x20000         /* block aligned */
 216 #define CONFIG_SYS_NAND_U_BOOT_OFFS     CONFIG_SPL_PAD_TO
 217 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (640 << 10)
 218 #endif
 219
 220 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 221 #define CONFIG_QIXIS_I2C_ACCESS
 222 #define CONFIG_SYS_I2C_EARLY_INIT
 223 #define CONFIG_SYS_NO_FLASH
 224 #endif
 225
 226 /*
 227  * QIXIS Definitions
 228  */
 229 #define CONFIG_FSL_QIXIS
 230
 231 #ifdef CONFIG_FSL_QIXIS
 232 #define QIXIS_BASE                      0x7fb00000
 233 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 234 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 235 #define QIXIS_LBMAP_SWITCH              6
 236 #define QIXIS_LBMAP_MASK                0x0f
 237 #define QIXIS_LBMAP_SHIFT               0
 238 #define QIXIS_LBMAP_DFLTBANK            0x00
 239 #define QIXIS_LBMAP_ALTBANK             0x04
 240 #define QIXIS_LBMAP_NAND                0x09
 241 #define QIXIS_LBMAP_SD                  0x00
 242 #define QIXIS_LBMAP_SD_QSPI             0xff
 243 #define QIXIS_LBMAP_QSPI                0xff
 244 #define QIXIS_RCW_SRC_NAND              0x106
 245 #define QIXIS_RCW_SRC_SD                0x040
 246 #define QIXIS_RCW_SRC_QSPI              0x045
 247 #define QIXIS_RST_CTL_RESET             0x41
 248 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 249 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 250 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 251
 252 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 253 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 254                                         CSPR_PORT_SIZE_8 | \
 255                                         CSPR_MSEL_GPCM | \
 256                                         CSPR_V)
 257 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 258 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 259                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 260                                         CSOR_NOR_TRHZ_80)
 261
 262 /*
 263  * QIXIS Timing parameters for IFC GPCM
 264  */
 265 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xc) | \
 266                                         FTIM0_GPCM_TEADC(0x20) | \
 267                                         FTIM0_GPCM_TEAHC(0x10))
 268 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0x50) | \
 269                                         FTIM1_GPCM_TRAD(0x1f))
 270 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0x8) | \
 271                                         FTIM2_GPCM_TCH(0x8) | \
 272                                         FTIM2_GPCM_TWP(0xf0))
 273 #define CONFIG_SYS_FPGA_FTIM3           0x0
 274 #endif
 275
 276 #ifdef CONFIG_NAND_BOOT
 277 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 278 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 279 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 280 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 281 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 282 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 283 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 284 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 285 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 286 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
 287 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 288 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 289 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 290 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 291 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 292 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 293 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 294 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR1_CSPR
 295 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 296 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 297 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 298 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 299 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 300 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 301 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 302 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 303 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 304 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 305 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 306 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 307 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 308 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 309 #else
 310 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 311 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 312 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 313 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 314 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 315 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 316 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 317 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 318 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 319 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 320 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 321 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 322 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 323 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 324 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 325 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 326 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 327 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 328 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 329 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 330 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 331 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 332 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 333 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 334 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 335 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 336 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 337 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 338 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 339 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 340 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 341 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 342 #endif
 343
 344 /*
 345  * I2C bus multiplexer
 346  */
 347 #define I2C_MUX_PCA_ADDR_PRI            0x77
 348 #define I2C_MUX_PCA_ADDR_SEC            0x76 /* Secondary multiplexer */
 349 #define I2C_RETIMER_ADDR                0x18
 350 #define I2C_MUX_CH_DEFAULT              0x8
 351 #define I2C_MUX_CH_CH7301               0xC
 352 #define I2C_MUX_CH5                     0xD
 353 #define I2C_MUX_CH7                     0xF
 354
 355 #define I2C_MUX_CH_VOL_MONITOR 0xa
 356
 357 /* Voltage monitor on channel 2*/
 358 #define I2C_VOL_MONITOR_ADDR           0x40
 359 #define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 360 #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 361 #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 362
 363 #define CONFIG_VID_FLS_ENV              "ls1043aqds_vdd_mv"
 364 #ifndef CONFIG_SPL_BUILD
 365 #define CONFIG_VID
 366 #endif
 367 #define CONFIG_VOL_MONITOR_IR36021_SET
 368 #define CONFIG_VOL_MONITOR_INA220
 369 /* The lowest and highest voltage allowed for LS1043AQDS */
 370 #define VDD_MV_MIN                      819
 371 #define VDD_MV_MAX                      1212
 372
 373 /* QSPI device */
 374 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 375 #define CONFIG_FSL_QSPI
 376 #ifdef CONFIG_FSL_QSPI
 377 #define CONFIG_SPI_FLASH_SPANSION
 378 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 379 #define FSL_QSPI_FLASH_NUM              2
 380 #endif
 381 #endif
 382
 383 /* USB */
 384 #define CONFIG_HAS_FSL_XHCI_USB
 385 #ifdef CONFIG_HAS_FSL_XHCI_USB
 386 #define CONFIG_USB_XHCI_FSL
 387 #define CONFIG_USB_MAX_CONTROLLER_COUNT         3
 388 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 389 #endif
 390
 391 /*
 392  * Miscellaneous configurable options
 393  */
 394 #define CONFIG_MISC_INIT_R
 395 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 396 #define CONFIG_AUTO_COMPLETE
 397 #define CONFIG_SYS_PBSIZE               \
 398                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 399 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 400
 401 #define CONFIG_SYS_MEMTEST_START        0x80000000
 402 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 403
 404 #define CONFIG_SYS_HZ                   1000
 405
 406 /*
 407  * Stack sizes
 408  * The stack sizes are set up in start.S using the settings below
 409  */
 410 #define CONFIG_STACKSIZE                (30 * 1024)
 411
 412 #define CONFIG_SYS_INIT_SP_OFFSET \
 413         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 414
 415 #ifdef CONFIG_SPL_BUILD
 416 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 417 #else
 418 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 419 #endif
 420
 421 /*
 422  * Environment
 423  */
 424 #define CONFIG_ENV_OVERWRITE
 425
 426 #ifdef CONFIG_NAND_BOOT
 427 #define CONFIG_ENV_IS_IN_NAND
 428 #define CONFIG_ENV_SIZE                 0x2000
 429 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 430 #elif defined(CONFIG_SD_BOOT)
 431 #define CONFIG_ENV_OFFSET               (1024 * 1024)
 432 #define CONFIG_ENV_IS_IN_MMC
 433 #define CONFIG_SYS_MMC_ENV_DEV          0
 434 #define CONFIG_ENV_SIZE                 0x2000
 435 #elif defined(CONFIG_QSPI_BOOT)
 436 #define CONFIG_ENV_IS_IN_SPI_FLASH
 437 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 438 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 439 #define CONFIG_ENV_SECT_SIZE            0x10000
 440 #else
 441 #define CONFIG_ENV_IS_IN_FLASH
 442 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 443 #define CONFIG_ENV_SECT_SIZE            0x20000
 444 #define CONFIG_ENV_SIZE                 0x20000
 445 #endif
 446
 447 #define CONFIG_CMDLINE_TAG
 448
 449 #include <asm/fsl_secure_boot.h>
 450
 451 #endif /* __LS1043AQDS_H__ */