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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/ls1046aqds.h
2 * Copyright 2016 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1046AQDS_H__
8 #define __LS1046AQDS_H__
10 #include "ls1046a_common.h"
12 #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT)
13 #define CONFIG_SYS_TEXT_BASE 0x82000000
14 #elif defined(CONFIG_QSPI_BOOT)
15 #define CONFIG_SYS_TEXT_BASE 0x40010000
17 #define CONFIG_SYS_TEXT_BASE 0x60100000
21 unsigned long get_board_sys_clk(void);
22 unsigned long get_board_ddr_clk(void);
25 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
26 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
28 #define CONFIG_SKIP_LOWLEVEL_INIT
30 #define CONFIG_LAYERSCAPE_NS_ACCESS
32 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
33 /* Physical Memory Map */
34 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
35 #define CONFIG_NR_DRAM_BANKS 2
37 #define CONFIG_DDR_SPD
38 #define SPD_EEPROM_ADDRESS 0x51
39 #define CONFIG_SYS_SPD_BUS_NUM 0
41 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
43 #define CONFIG_DDR_ECC
45 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
49 #define CONFIG_SYS_HAS_SERDES
52 #ifdef CONFIG_FSL_DSPI
53 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
54 #define CONFIG_SPI_FLASH_SST /* cs1 */
55 #define CONFIG_SPI_FLASH_EON /* cs2 */
56 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
57 #define CONFIG_SF_DEFAULT_BUS 1
58 #define CONFIG_SF_DEFAULT_CS 0
63 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
64 #ifdef CONFIG_FSL_QSPI
65 #define CONFIG_SPI_FLASH_SPANSION
66 #define FSL_QSPI_FLASH_SIZE (1 << 24)
67 #define FSL_QSPI_FLASH_NUM 2
71 #ifdef CONFIG_SYS_DPAA_FMAN
72 #define CONFIG_FMAN_ENET
74 #define CONFIG_PHY_VITESSE
75 #define CONFIG_PHY_REALTEK
76 #define CONFIG_PHYLIB_10G
77 #define RGMII_PHY1_ADDR 0x1
78 #define RGMII_PHY2_ADDR 0x2
79 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
80 #define SGMII_CARD_PORT2_PHY_ADDR 0x1D
81 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
82 #define SGMII_CARD_PORT4_PHY_ADDR 0x1F
83 /* PHY address on QSGMII riser card on slot 2 */
84 #define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8
85 #define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9
86 #define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA
87 #define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB
90 #ifdef CONFIG_RAMBOOT_PBL
91 #define CONFIG_SYS_FSL_PBL_PBI \
92 board/freescale/ls1046aqds/ls1046aqds_pbi.cfg
95 #ifdef CONFIG_NAND_BOOT
96 #define CONFIG_SYS_FSL_PBL_RCW \
97 board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg
100 #ifdef CONFIG_SD_BOOT
101 #ifdef CONFIG_SD_BOOT_QSPI
102 #define CONFIG_SYS_FSL_PBL_RCW \
103 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg
105 #define CONFIG_SYS_FSL_PBL_RCW \
106 board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg
111 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
112 #define CONFIG_FSL_IFC
114 * CONFIG_SYS_FLASH_BASE has the final address (core view)
115 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
116 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
117 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
119 #define CONFIG_SYS_FLASH_BASE 0x60000000
120 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
121 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
123 #ifndef CONFIG_SYS_NO_FLASH
124 #define CONFIG_FLASH_CFI_DRIVER
125 #define CONFIG_SYS_FLASH_CFI
126 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
127 #define CONFIG_SYS_FLASH_QUIET_TEST
128 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
133 #define CONFIG_LIBATA
134 #define CONFIG_SCSI_AHCI
135 #define CONFIG_SCSI_AHCI_PLAT
137 #define CONFIG_DOS_PARTITION
138 #define CONFIG_BOARD_LATE_INIT
141 #define CONFIG_ID_EEPROM
142 #define CONFIG_SYS_I2C_EEPROM_NXID
143 #define CONFIG_SYS_EEPROM_BUS_NUM 0
144 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
145 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
146 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
147 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
149 #define CONFIG_SYS_SATA AHCI_BASE_ADDR
151 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
152 #define CONFIG_SYS_SCSI_MAX_LUN 1
153 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
154 CONFIG_SYS_SCSI_MAX_LUN)
159 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
160 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
161 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
162 CSPR_PORT_SIZE_16 | \
165 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
166 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
168 CSPR_PORT_SIZE_16 | \
171 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
173 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
175 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
176 FTIM0_NOR_TEADC(0x5) | \
177 FTIM0_NOR_TEAHC(0x5))
178 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
179 FTIM1_NOR_TRAD_NOR(0x1a) | \
180 FTIM1_NOR_TSEQRAD_NOR(0x13))
181 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
182 FTIM2_NOR_TCH(0x4) | \
183 FTIM2_NOR_TWPH(0xe) | \
185 #define CONFIG_SYS_NOR_FTIM3 0
187 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
188 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
189 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
190 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
192 #define CONFIG_SYS_FLASH_EMPTY_INFO
193 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
194 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
196 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
197 #define CONFIG_SYS_WRITE_SWAPPED_DATA
200 * NAND Flash Definitions
202 #define CONFIG_NAND_FSL_IFC
204 #define CONFIG_SYS_NAND_BASE 0x7e800000
205 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
207 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
209 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
213 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
214 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
215 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
216 | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \
217 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
218 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
219 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
220 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
222 #define CONFIG_SYS_NAND_ONFI_DETECTION
224 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
225 FTIM0_NAND_TWP(0x18) | \
226 FTIM0_NAND_TWCHT(0x7) | \
228 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
229 FTIM1_NAND_TWBE(0x39) | \
230 FTIM1_NAND_TRR(0xe) | \
231 FTIM1_NAND_TRP(0x18))
232 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
233 FTIM2_NAND_TREH(0xa) | \
234 FTIM2_NAND_TWHRE(0x1e))
235 #define CONFIG_SYS_NAND_FTIM3 0x0
237 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
238 #define CONFIG_SYS_MAX_NAND_DEVICE 1
239 #define CONFIG_MTD_NAND_VERIFY_WRITE
240 #define CONFIG_CMD_NAND
242 #define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
245 #ifdef CONFIG_NAND_BOOT
246 #define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */
247 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
248 #define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
251 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
252 #define CONFIG_QIXIS_I2C_ACCESS
253 #define CONFIG_SYS_I2C_EARLY_INIT
254 #define CONFIG_SYS_NO_FLASH
260 #define CONFIG_FSL_QIXIS
262 #ifdef CONFIG_FSL_QIXIS
263 #define QIXIS_BASE 0x7fb00000
264 #define QIXIS_BASE_PHYS QIXIS_BASE
265 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
266 #define QIXIS_LBMAP_SWITCH 6
267 #define QIXIS_LBMAP_MASK 0x0f
268 #define QIXIS_LBMAP_SHIFT 0
269 #define QIXIS_LBMAP_DFLTBANK 0x00
270 #define QIXIS_LBMAP_ALTBANK 0x04
271 #define QIXIS_LBMAP_NAND 0x09
272 #define QIXIS_LBMAP_SD 0x00
273 #define QIXIS_LBMAP_SD_QSPI 0xff
274 #define QIXIS_LBMAP_QSPI 0xff
275 #define QIXIS_RCW_SRC_NAND 0x110
276 #define QIXIS_RCW_SRC_SD 0x040
277 #define QIXIS_RCW_SRC_QSPI 0x045
278 #define QIXIS_RST_CTL_RESET 0x41
279 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
280 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
281 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
283 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
284 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
288 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
289 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
290 CSOR_NOR_NOR_MODE_AVD_NOR | \
294 * QIXIS Timing parameters for IFC GPCM
296 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \
297 FTIM0_GPCM_TEADC(0x20) | \
298 FTIM0_GPCM_TEAHC(0x10))
299 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \
300 FTIM1_GPCM_TRAD(0x1f))
301 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \
302 FTIM2_GPCM_TCH(0x8) | \
303 FTIM2_GPCM_TWP(0xf0))
304 #define CONFIG_SYS_FPGA_FTIM3 0x0
307 #ifdef CONFIG_NAND_BOOT
308 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
309 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
310 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
311 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
312 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
313 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
314 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
315 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
316 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
317 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
318 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
319 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
320 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
321 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
322 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
323 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
324 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
325 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
326 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
327 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
328 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
329 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
330 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
331 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
332 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
333 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
334 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
335 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
336 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
337 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
338 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
339 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
341 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
342 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
343 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
344 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
345 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
346 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
347 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
348 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
349 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
350 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
351 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
352 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
353 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
354 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
355 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
356 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
357 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
358 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
359 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
360 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
361 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
362 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
363 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
364 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
365 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
366 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
367 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
368 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
369 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
370 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
371 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
372 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
376 * I2C bus multiplexer
378 #define I2C_MUX_PCA_ADDR_PRI 0x77
379 #define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
380 #define I2C_RETIMER_ADDR 0x18
381 #define I2C_MUX_CH_DEFAULT 0x8
382 #define I2C_MUX_CH_CH7301 0xC
383 #define I2C_MUX_CH5 0xD
384 #define I2C_MUX_CH6 0xE
385 #define I2C_MUX_CH7 0xF
387 #define I2C_MUX_CH_VOL_MONITOR 0xa
389 /* Voltage monitor on channel 2*/
390 #define I2C_VOL_MONITOR_ADDR 0x40
391 #define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
392 #define I2C_VOL_MONITOR_BUS_V_OVF 0x1
393 #define I2C_VOL_MONITOR_BUS_V_SHIFT 3
395 #define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv"
396 #ifndef CONFIG_SPL_BUILD
399 #define CONFIG_VOL_MONITOR_IR36021_SET
400 #define CONFIG_VOL_MONITOR_INA220
401 /* The lowest and highest voltage allowed for LS1046AQDS */
402 #define VDD_MV_MIN 819
403 #define VDD_MV_MAX 1212
406 * Miscellaneous configurable options
408 #define CONFIG_MISC_INIT_R
409 #define CONFIG_SYS_LONGHELP /* undef to save memory */
410 #define CONFIG_AUTO_COMPLETE
411 #define CONFIG_SYS_PBSIZE \
412 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
413 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
415 #define CONFIG_SYS_MEMTEST_START 0x80000000
416 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
418 #define CONFIG_SYS_HZ 1000
422 * The stack sizes are set up in start.S using the settings below
424 #define CONFIG_STACKSIZE (30 * 1024)
426 #define CONFIG_SYS_INIT_SP_OFFSET \
427 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
429 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
434 #define CONFIG_ENV_OVERWRITE
436 #ifdef CONFIG_NAND_BOOT
437 #define CONFIG_ENV_IS_IN_NAND
438 #define CONFIG_ENV_SIZE 0x2000
439 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
440 #elif defined(CONFIG_SD_BOOT)
441 #define CONFIG_ENV_OFFSET (1024 * 1024)
442 #define CONFIG_ENV_IS_IN_MMC
443 #define CONFIG_SYS_MMC_ENV_DEV 0
444 #define CONFIG_ENV_SIZE 0x2000
445 #elif defined(CONFIG_QSPI_BOOT)
446 #define CONFIG_ENV_IS_IN_SPI_FLASH
447 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
448 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
449 #define CONFIG_ENV_SECT_SIZE 0x10000
451 #define CONFIG_ENV_IS_IN_FLASH
452 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
453 #define CONFIG_ENV_SECT_SIZE 0x20000
454 #define CONFIG_ENV_SIZE 0x20000
457 #define CONFIG_CMDLINE_TAG
459 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
460 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
461 "e0000 f00000 && bootm $kernel_load"
463 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
464 "$kernel_size && bootm $kernel_load"
467 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
468 #define MTDPARTS_DEFAULT "mtdparts=1550000.quadspi:2m(uboot)," \
471 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
472 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
473 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
474 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
475 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
476 "40m(nor_bank4_fit);7e800000.flash:" \
477 "4m(nand_uboot),36m(nand_kernel)," \
478 "472m(nand_free);spi0.0:2m(uboot)," \
482 #include <asm/fsl_secure_boot.h>
484 #endif /* __LS1046AQDS_H__ */