include/configs/ls2080a_common.h

   1 /*
   2  * Copyright (C) 2014 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_COMMON_H
   8 #define __LS2_COMMON_H
   9
  10 #define CONFIG_REMAKE_ELF
  11 #define CONFIG_FSL_LAYERSCAPE
  12 #define CONFIG_FSL_LSCH3
  13 #define CONFIG_MP
  14 #define CONFIG_GICV3
  15 #define CONFIG_FSL_TZPC_BP147
  16
  17 #include <asm/arch/ls2080a_stream_id.h>
  18 #include <asm/arch/config.h>
  19 #if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2))
  20 #define CONFIG_SYS_HAS_SERDES
  21 #endif
  22
  23 /* Link Definitions */
  24 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  25
  26 /* We need architecture specific misc initializations */
  27 #define CONFIG_ARCH_MISC_INIT
  28
  29 /* Link Definitions */
  30 #ifdef CONFIG_SPL
  31 #define CONFIG_SYS_TEXT_BASE            0x80400000
  32 #else
  33 #define CONFIG_SYS_TEXT_BASE            0x30100000
  34 #endif
  35
  36 #ifdef CONFIG_EMU
  37 #define CONFIG_SYS_NO_FLASH
  38 #endif
  39
  40 #define CONFIG_SUPPORT_RAW_INITRD
  41
  42 #define CONFIG_SKIP_LOWLEVEL_INIT
  43 #define CONFIG_BOARD_EARLY_INIT_F       1
  44
  45 #ifndef CONFIG_SPL
  46 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  47 #endif
  48 #ifndef CONFIG_SYS_FSL_DDR4
  49 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
  50 #define CONFIG_SYS_DDR_RAW_TIMING
  51 #endif
  52
  53 #define CONFIG_SYS_FSL_DDR_INTLV_256B   /* force 256 byte interleaving */
  54
  55 #define CONFIG_VERY_BIG_RAM
  56 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  57 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  58 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  59 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x8080000000ULL
  60 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       2
  61
  62 /*
  63  * SMP Definitinos
  64  */
  65 #define CPU_RELEASE_ADDR                secondary_boot_func
  66
  67 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
  68 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  69 #define CONFIG_SYS_DP_DDR_BASE          0x6000000000ULL
  70 /*
  71  * DDR controller use 0 as the base address for binding.
  72  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
  73  */
  74 #define CONFIG_SYS_DP_DDR_BASE_PHY      0
  75 #define CONFIG_DP_DDR_CTRL              2
  76 #define CONFIG_DP_DDR_NUM_CTRLS         1
  77 #endif
  78
  79 /* Generic Timer Definitions */
  80 /*
  81  * This is not an accurate number. It is used in start.S. The frequency
  82  * will be udpated later when get_bus_freq(0) is available.
  83  */
  84 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  85
  86 /* Size of malloc() pool */
  87 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 2048 * 1024)
  88
  89 /* I2C */
  90 #define CONFIG_SYS_I2C
  91 #define CONFIG_SYS_I2C_MXC
  92 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
  93 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
  94 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
  95 #define CONFIG_SYS_I2C_MXC_I2C4         /* enable I2C bus 4 */
  96
  97 /* Serial Port */
  98 #define CONFIG_CONS_INDEX       1
  99 #define CONFIG_SYS_NS16550_SERIAL
 100 #define CONFIG_SYS_NS16550_REG_SIZE     1
 101 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 102
 103 #define CONFIG_BAUDRATE                 115200
 104 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 105
 106 /* IFC */
 107 #define CONFIG_FSL_IFC
 108
 109 /*
 110  * During booting, IFC is mapped at the region of 0x30000000.
 111  * But this region is limited to 256MB. To accommodate NOR, promjet
 112  * and FPGA. This region is divided as below:
 113  * 0x30000000 - 0x37ffffff : 128MB : NOR flash
 114  * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
 115  * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
 116  *
 117  * To accommodate bigger NOR flash and other devices, we will map IFC
 118  * chip selects to as below:
 119  * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
 120  * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
 121  * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
 122  * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
 123  * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
 124  *
 125  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
 126  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 127  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 128  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 129  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 130  */
 131
 132 #define CONFIG_SYS_FLASH_BASE                   0x580000000ULL
 133 #define CONFIG_SYS_FLASH_BASE_PHYS              0x80000000
 134 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 135
 136 #define CONFIG_SYS_FLASH1_BASE_PHYS             0xC0000000
 137 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY       0x8000000
 138
 139 #ifndef CONFIG_SYS_NO_FLASH
 140 #define CONFIG_FLASH_CFI_DRIVER
 141 #define CONFIG_SYS_FLASH_CFI
 142 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 143 #define CONFIG_SYS_FLASH_QUIET_TEST
 144 #endif
 145
 146 #ifndef __ASSEMBLY__
 147 unsigned long long get_qixis_addr(void);
 148 #endif
 149 #define QIXIS_BASE                              get_qixis_addr()
 150 #define QIXIS_BASE_PHYS                         0x20000000
 151 #define QIXIS_BASE_PHYS_EARLY                   0xC000000
 152 #define QIXIS_STAT_PRES1                        0xb
 153 #define QIXIS_SDID_MASK                         0x07
 154 #define QIXIS_ESDHC_NO_ADAPTER                  0x7
 155
 156 #define CONFIG_SYS_NAND_BASE                    0x530000000ULL
 157 #define CONFIG_SYS_NAND_BASE_PHYS               0x30000000
 158
 159 /* Debug Server firmware */
 160 #define CONFIG_FSL_DEBUG_SERVER
 161 /* 2 sec timeout */
 162 #define CONFIG_SYS_DEBUG_SERVER_TIMEOUT                 (2 * 1000 * 1000)
 163
 164 /* MC firmware */
 165 #define CONFIG_FSL_MC_ENET
 166 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
 167 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH     0x20000
 168 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 169 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH     0x20000
 170 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
 171 /* For LS2085A */
 172 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH    0x200000
 173 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET   0x07000000
 174
 175 /*
 176  * Carve out a DDR region which will not be used by u-boot/Linux
 177  *
 178  * It will be used by MC and Debug Server. The MC region must be
 179  * 512MB aligned, so the min size to hide is 512MB.
 180  */
 181 #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER)
 182 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE     (254UL * 1024 * 1024)
 183 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE            (512UL * 1024 * 1024)
 184 #define CONFIG_SYS_MC_RSV_MEM_ALIGN                     (512UL * 1024 * 1024)
 185 #endif
 186
 187 /* PCIe */
 188 #define CONFIG_PCIE1            /* PCIE controler 1 */
 189 #define CONFIG_PCIE2            /* PCIE controler 2 */
 190 #define CONFIG_PCIE3            /* PCIE controler 3 */
 191 #define CONFIG_PCIE4            /* PCIE controler 4 */
 192 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 193 #ifdef CONFIG_LS2080A
 194 #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
 195 #endif
 196
 197 #define CONFIG_SYS_PCI_64BIT
 198
 199 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF   0x00000000
 200 #define CONFIG_SYS_PCIE_CFG0_SIZE       0x00001000      /* 4k */
 201 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF   0x00001000
 202 #define CONFIG_SYS_PCIE_CFG1_SIZE       0x00001000      /* 4k */
 203
 204 #define CONFIG_SYS_PCIE_IO_BUS          0x00000000
 205 #define CONFIG_SYS_PCIE_IO_PHYS_OFF     0x00010000
 206 #define CONFIG_SYS_PCIE_IO_SIZE         0x00010000      /* 64k */
 207
 208 #define CONFIG_SYS_PCIE_MEM_BUS         0x40000000
 209 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x40000000
 210 #define CONFIG_SYS_PCIE_MEM_SIZE        0x40000000      /* 1G */
 211
 212 /* Command line configuration */
 213 #define CONFIG_CMD_CACHE
 214 #define CONFIG_CMD_ENV
 215 #define CONFIG_CMD_GREPENV
 216 #define CONFIG_CMD_MII
 217
 218 /* Miscellaneous configurable options */
 219 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 220 #define CONFIG_ARCH_EARLY_INIT_R
 221
 222 /* Physical Memory Map */
 223 /* fixme: these need to be checked against the board */
 224 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 225
 226 #define CONFIG_NR_DRAM_BANKS            3
 227
 228 #define CONFIG_HWCONFIG
 229 #define HWCONFIG_BUFFER_SIZE            128
 230
 231 #define CONFIG_DISPLAY_CPUINFO
 232
 233 /* Allow to overwrite serial and ethaddr */
 234 #define CONFIG_ENV_OVERWRITE
 235
 236 /* Initial environment variables */
 237 #define CONFIG_EXTRA_ENV_SETTINGS               \
 238         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 239         "loadaddr=0x80100000\0"                 \
 240         "kernel_addr=0x100000\0"                \
 241         "ramdisk_addr=0x800000\0"               \
 242         "ramdisk_size=0x2000000\0"              \
 243         "fdt_high=0xa0000000\0"                 \
 244         "initrd_high=0xffffffffffffffff\0"      \
 245         "kernel_start=0x581200000\0"            \
 246         "kernel_load=0xa0000000\0"              \
 247         "kernel_size=0x2800000\0"               \
 248         "console=ttyAMA0,38400n8\0"             \
 249         "mcinitcmd=fsl_mc start mc 0x580300000" \
 250         " 0x580800000 \0"
 251
 252 #define CONFIG_BOOTARGS         "console=ttyS0,115200 root=/dev/ram0 " \
 253                                 "earlycon=uart8250,mmio,0x21c0500 " \
 254                                 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
 255                                 " hugepagesz=2m hugepages=256"
 256 #define CONFIG_BOOTCOMMAND      "fsl_mc apply dpl 0x580700000 &&" \
 257                                 " cp.b $kernel_start $kernel_load" \
 258                                 " $kernel_size && bootm $kernel_load"
 259 #define CONFIG_BOOTDELAY                10
 260
 261 /* Monitor Command Prompt */
 262 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 263 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 264                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 265 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 266 #define CONFIG_SYS_LONGHELP
 267 #define CONFIG_CMDLINE_EDITING          1
 268 #define CONFIG_AUTO_COMPLETE
 269 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 270
 271 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 272
 273 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 274 #define CONFIG_SPL_BSS_MAX_SIZE         0x00100000
 275 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 276 #define CONFIG_SPL_ENV_SUPPORT
 277 #define CONFIG_SPL_FRAMEWORK
 278 #define CONFIG_SPL_I2C_SUPPORT
 279 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
 280 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 281 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 282 #define CONFIG_SPL_MAX_SIZE             0x16000
 283 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
 284 #define CONFIG_SPL_NAND_SUPPORT
 285 #define CONFIG_SPL_SERIAL_SUPPORT
 286 #define CONFIG_SPL_STACK                (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
 287 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 288 #define CONFIG_SPL_TEXT_BASE            0x1800a000
 289
 290 #define CONFIG_SYS_NAND_U_BOOT_DST      0x80400000
 291 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 292 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x00100000
 293 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 294 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)
 295
 296 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 297
 298 #endif /* __LS2_COMMON_H */