include/configs/ls2085ardb.h

   1 /*
   2  * Copyright 2015 Freescale Semiconductor
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __LS2_RDB_H
   8 #define __LS2_RDB_H
   9
  10 #include "ls2085a_common.h"
  11 #define CONFIG_IDENT_STRING             " LS2085A-RDB"
  12 #define CONFIG_BOOTP_VCI_STRING         "U-boot.LS2085A-RDB"
  13
  14 #undef CONFIG_CONS_INDEX
  15 #define CONFIG_CONS_INDEX       2
  16
  17 #define CONFIG_DISPLAY_BOARDINFO
  18
  19 #ifndef __ASSEMBLY__
  20 unsigned long get_board_sys_clk(void);
  21 #endif
  22
  23 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  24 #define CONFIG_DDR_CLK_FREQ             133333333
  25 #define COUNTER_FREQUENCY_REAL          (CONFIG_SYS_CLK_FREQ/4)
  26
  27 #define CONFIG_DDR_SPD
  28 #define CONFIG_DDR_ECC
  29 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  30 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
  31 #define SPD_EEPROM_ADDRESS1     0x51
  32 #define SPD_EEPROM_ADDRESS2     0x52
  33 #define SPD_EEPROM_ADDRESS3     0x54
  34 #define SPD_EEPROM_ADDRESS4     0x53    /* Board error */
  35 #define SPD_EEPROM_ADDRESS5     0x55
  36 #define SPD_EEPROM_ADDRESS6     0x56    /* dummy address */
  37 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
  38 #define CONFIG_SYS_SPD_BUS_NUM  0       /* SPD on I2C bus 0 */
  39 #define CONFIG_DIMM_SLOTS_PER_CTLR              2
  40 #define CONFIG_CHIP_SELECTS_PER_CTRL            4
  41 #define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR       1
  42 #define CONFIG_FSL_DDR_BIST     /* enable built-in memory test */
  43
  44 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
  45
  46 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
  47 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128*1024*1024)
  48 #define CONFIG_SYS_NOR_AMASK_EARLY      IFC_AMASK(64*1024*1024)
  49
  50 #define CONFIG_SYS_NOR0_CSPR                                    \
  51         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
  52         CSPR_PORT_SIZE_16                                       | \
  53         CSPR_MSEL_NOR                                           | \
  54         CSPR_V)
  55 #define CONFIG_SYS_NOR0_CSPR_EARLY                              \
  56         (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
  57         CSPR_PORT_SIZE_16                                       | \
  58         CSPR_MSEL_NOR                                           | \
  59         CSPR_V)
  60 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(12)
  61 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
  62                                 FTIM0_NOR_TEADC(0x5) | \
  63                                 FTIM0_NOR_TEAHC(0x5))
  64 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
  65                                 FTIM1_NOR_TRAD_NOR(0x1a) |\
  66                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
  67 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
  68                                 FTIM2_NOR_TCH(0x4) | \
  69                                 FTIM2_NOR_TWPH(0x0E) | \
  70                                 FTIM2_NOR_TWP(0x1c))
  71 #define CONFIG_SYS_NOR_FTIM3    0x04000000
  72 #define CONFIG_SYS_IFC_CCR      0x01000000
  73
  74 #ifndef CONFIG_SYS_NO_FLASH
  75 #define CONFIG_FLASH_CFI_DRIVER
  76 #define CONFIG_SYS_FLASH_CFI
  77 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  78 #define CONFIG_SYS_FLASH_QUIET_TEST
  79 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
  80
  81 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
  82 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
  83 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
  84 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
  85
  86 #define CONFIG_SYS_FLASH_EMPTY_INFO
  87 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE,\
  88                                          CONFIG_SYS_FLASH_BASE + 0x40000000}
  89 #endif
  90
  91 #define CONFIG_NAND_FSL_IFC
  92 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
  93 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
  94
  95
  96 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
  97 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
  98                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
  99                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 100                                 | CSPR_V)
 101 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 102
 103 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 104                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 105                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 106                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
 107                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
 108                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
 109                                 | CSOR_NAND_PB(128))    /* Pages Per Block 128*/
 110
 111 #define CONFIG_SYS_NAND_ONFI_DETECTION
 112
 113 /* ONFI NAND Flash mode0 Timing Params */
 114 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x0e) | \
 115                                         FTIM0_NAND_TWP(0x30)   | \
 116                                         FTIM0_NAND_TWCHT(0x0e) | \
 117                                         FTIM0_NAND_TWH(0x14))
 118 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x64) | \
 119                                         FTIM1_NAND_TWBE(0xab)  | \
 120                                         FTIM1_NAND_TRR(0x1c)   | \
 121                                         FTIM1_NAND_TRP(0x30))
 122 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x1e) | \
 123                                         FTIM2_NAND_TREH(0x14) | \
 124                                         FTIM2_NAND_TWHRE(0x3c))
 125 #define CONFIG_SYS_NAND_FTIM3           0x0
 126
 127 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 128 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 129 #define CONFIG_MTD_NAND_VERIFY_WRITE
 130 #define CONFIG_CMD_NAND
 131
 132 #define CONFIG_SYS_NAND_BLOCK_SIZE      (512 * 1024)
 133
 134 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 135 #define QIXIS_LBMAP_SWITCH              0x06
 136 #define QIXIS_LBMAP_MASK                0x0f
 137 #define QIXIS_LBMAP_SHIFT               0
 138 #define QIXIS_LBMAP_DFLTBANK            0x00
 139 #define QIXIS_LBMAP_ALTBANK             0x04
 140 #define QIXIS_LBMAP_NAND                0x09
 141 #define QIXIS_RST_CTL_RESET             0x31
 142 #define QIXIS_RST_CTL_RESET_EN          0x30
 143 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 144 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 145 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 146 #define QIXIS_RCW_SRC_NAND              0x119
 147 #define QIXIS_RST_FORCE_MEM             0x01
 148
 149 #define CONFIG_SYS_CSPR3_EXT    (0x0)
 150 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
 151                                 | CSPR_PORT_SIZE_8 \
 152                                 | CSPR_MSEL_GPCM \
 153                                 | CSPR_V)
 154 #define CONFIG_SYS_CSPR3_FINAL  (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 155                                 | CSPR_PORT_SIZE_8 \
 156                                 | CSPR_MSEL_GPCM \
 157                                 | CSPR_V)
 158
 159 #define CONFIG_SYS_AMASK3       IFC_AMASK(64*1024)
 160 #define CONFIG_SYS_CSOR3        CSOR_GPCM_ADM_SHIFT(12)
 161 /* QIXIS Timing parameters for IFC CS3 */
 162 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 163                                         FTIM0_GPCM_TEADC(0x0e) | \
 164                                         FTIM0_GPCM_TEAHC(0x0e))
 165 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0xff) | \
 166                                         FTIM1_GPCM_TRAD(0x3f))
 167 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0xf) | \
 168                                         FTIM2_GPCM_TCH(0xf) | \
 169                                         FTIM2_GPCM_TWP(0x3E))
 170 #define CONFIG_SYS_CS3_FTIM3            0x0
 171
 172 #if defined(CONFIG_SPL) && defined(CONFIG_NAND)
 173 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 174 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR_EARLY
 175 #define CONFIG_SYS_CSPR2_FINAL          CONFIG_SYS_NOR0_CSPR
 176 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 177 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 178 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 179 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 180 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 181 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 182 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 183 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 184 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 185 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 186 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 187 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 188 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 189 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 190
 191 #define CONFIG_ENV_IS_IN_NAND
 192 #define CONFIG_ENV_OFFSET               (2048 * 1024)
 193 #define CONFIG_ENV_SECT_SIZE            0x20000
 194 #define CONFIG_ENV_SIZE                 0x2000
 195 #define CONFIG_SPL_PAD_TO               0x80000
 196 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (1024 * 1024)
 197 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (512 * 1024)
 198 #else
 199 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 200 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR_EARLY
 201 #define CONFIG_SYS_CSPR0_FINAL          CONFIG_SYS_NOR0_CSPR
 202 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 203 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 204 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 205 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 206 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 207 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 208 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 209 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 210 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 211 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 212 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 213 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 214 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 215 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 216
 217 #define CONFIG_ENV_IS_IN_FLASH
 218 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x200000)
 219 #define CONFIG_ENV_SECT_SIZE            0x20000
 220 #define CONFIG_ENV_SIZE                 0x2000
 221 #endif
 222
 223 /* Debug Server firmware */
 224 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
 225 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
 226
 227 /* MC firmware */
 228 #define CONFIG_SYS_LS_MC_FW_IN_NOR
 229 #define CONFIG_SYS_LS_MC_FW_ADDR        0x580300000ULL
 230
 231 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
 232 #define CONFIG_SYS_LS_MC_DPL_ADDR       0x580700000ULL
 233
 234 #define CONFIG_SYS_LS_MC_DPC_IN_NOR
 235 #define CONFIG_SYS_LS_MC_DPC_ADDR       0x580800000ULL
 236
 237 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
 238
 239 /*
 240  * I2C
 241  */
 242 #define I2C_MUX_PCA_ADDR                0x77
 243 #define I2C_MUX_PCA_ADDR_PRI            0x77 /* Primary Mux*/
 244
 245 /* I2C bus multiplexer */
 246 #define I2C_MUX_CH_DEFAULT      0x8
 247
 248 /*
 249  * RTC configuration
 250  */
 251 #define RTC
 252 #define CONFIG_RTC_DS3231               1
 253 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 254
 255 /* EEPROM */
 256 #define CONFIG_ID_EEPROM
 257 #define CONFIG_CMD_EEPROM
 258 #define CONFIG_SYS_I2C_EEPROM_NXID
 259 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 260 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 261 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 262 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 263 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 264
 265 #define CONFIG_FSL_MEMAC
 266 #define CONFIG_PCI              /* Enable PCIE */
 267 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 268
 269 #ifdef CONFIG_PCI
 270 #define CONFIG_PCI_PNP
 271 #define CONFIG_E1000
 272 #define CONFIG_PCI_SCAN_SHOW
 273 #define CONFIG_CMD_PCI
 274 #endif
 275
 276 /*  MMC  */
 277 #define CONFIG_MMC
 278 #ifdef CONFIG_MMC
 279 #define CONFIG_CMD_MMC
 280 #define CONFIG_FSL_ESDHC
 281 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 282 #define CONFIG_GENERIC_MMC
 283 #define CONFIG_CMD_FAT
 284 #define CONFIG_DOS_PARTITION
 285 #endif
 286
 287 /* Initial environment variables */
 288 #undef CONFIG_EXTRA_ENV_SETTINGS
 289 #define CONFIG_EXTRA_ENV_SETTINGS               \
 290         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 291         "loadaddr=0x80100000\0"                 \
 292         "kernel_addr=0x100000\0"                \
 293         "ramdisk_addr=0x800000\0"               \
 294         "ramdisk_size=0x2000000\0"              \
 295         "fdt_high=0xa0000000\0"                 \
 296         "initrd_high=0xffffffffffffffff\0"      \
 297         "kernel_start=0x581100000\0"            \
 298         "kernel_load=0xa0000000\0"              \
 299         "kernel_size=0x1000000\0"
 300
 301 #endif /* __LS2_RDB_H */