include/configs/lubbock.h

   1 /*
   2  * (C) Copyright 2002
   3  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
   4  *
   5  * (C) Copyright 2002
   6  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   7  * Marius Groeger <mgroeger@sysgo.de>
   8  *
   9  * Configuation settings for the LUBBOCK board.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_PXA250           1       /* This is an PXA250 CPU    */
  38 #define CONFIG_LUBBOCK          1       /* on an LUBBOCK Board      */
  39 #define CONFIG_LCD              1
  40 #ifdef CONFIG_LCD
  41 #define CONFIG_SHARP_LM8V31
  42 #endif
  43 #define CONFIG_MMC              1
  44 #define BOARD_LATE_INIT         1
  45
  46 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  47
  48 /*
  49  * Size of malloc() pool
  50  */
  51 #define CFG_MALLOC_LEN      (CFG_ENV_SIZE + 128*1024)
  52 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
  53
  54 /*
  55  * Hardware drivers
  56  */
  57 #define CONFIG_DRIVER_LAN91C96
  58 #define CONFIG_LAN91C96_BASE 0x0C000000
  59
  60 /*
  61  * select serial console configuration
  62  */
  63 #define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
  64
  65 /* allow to overwrite serial and ethaddr */
  66 #define CONFIG_ENV_OVERWRITE
  67
  68 #define CONFIG_BAUDRATE         115200
  69
  70
  71 /*
  72  * BOOTP options
  73  */
  74 #define CONFIG_BOOTP_BOOTFILESIZE
  75 #define CONFIG_BOOTP_BOOTPATH
  76 #define CONFIG_BOOTP_GATEWAY
  77 #define CONFIG_BOOTP_HOSTNAME
  78
  79
  80 /*
  81  * Command line configuration.
  82  */
  83 #include <config_cmd_default.h>
  84
  85 #define CONFIG_CMD_MMC
  86 #define CONFIG_CMD_FAT
  87
  88
  89 #define CONFIG_BOOTDELAY        3
  90 #define CONFIG_ETHADDR          08:00:3e:26:0a:5b
  91 #define CONFIG_NETMASK          255.255.0.0
  92 #define CONFIG_IPADDR           192.168.0.21
  93 #define CONFIG_SERVERIP         192.168.0.250
  94 #define CONFIG_BOOTCOMMAND      "bootm 80000"
  95 #define CONFIG_BOOTARGS         "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
  96 #define CONFIG_CMDLINE_TAG
  97 #define CONFIG_TIMESTAMP
  98
  99 #if defined(CONFIG_CMD_KGDB)
 100 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 101 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 102 #endif
 103
 104 /*
 105  * Miscellaneous configurable options
 106  */
 107 #define CFG_HUSH_PARSER         1
 108 #define CFG_PROMPT_HUSH_PS2     "> "
 109
 110 #define CFG_LONGHELP                            /* undef to save memory         */
 111 #ifdef CFG_HUSH_PARSER
 112 #define CFG_PROMPT              "$ "            /* Monitor Command Prompt */
 113 #else
 114 #define CFG_PROMPT              "=> "           /* Monitor Command Prompt */
 115 #endif
 116 #define CFG_CBSIZE              256             /* Console I/O Buffer Size      */
 117 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 118 #define CFG_MAXARGS             16              /* max number of command args   */
 119 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 120 #define CFG_DEVICE_NULLDEV      1
 121
 122 #define CFG_MEMTEST_START       0xa0400000      /* memtest works on     */
 123 #define CFG_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 124
 125 #undef  CFG_CLKS_IN_HZ          /* everything, incl board info, in Hz */
 126
 127 #define CFG_LOAD_ADDR   (CFG_DRAM_BASE + 0x8000) /* default load address */
 128
 129 #define CFG_HZ                  3686400         /* incrementer freq: 3.6864 MHz */
 130 #define CFG_CPUSPEED            0x161           /* set core clock to 400/200/100 MHz */
 131
 132                                                 /* valid baudrates */
 133 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 134
 135 #define CFG_MMC_BASE            0xF0000000
 136
 137 /*
 138  * Stack sizes
 139  *
 140  * The stack sizes are set up in start.S using the settings below
 141  */
 142 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 143 #ifdef CONFIG_USE_IRQ
 144 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 145 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 146 #endif
 147
 148 /*
 149  * Physical Memory Map
 150  */
 151 #define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
 152 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 153 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 154 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 155 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 156 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 157 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 158 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 159 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 160
 161 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 162 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #2 */
 163 #define PHYS_FLASH_SIZE         0x02000000 /* 32 MB */
 164 #define PHYS_FLASH_BANK_SIZE    0x02000000 /* 32 MB Banks */
 165 #define PHYS_FLASH_SECT_SIZE    0x00040000 /* 256 KB sectors (x2) */
 166
 167 #define CFG_DRAM_BASE           0xa0000000
 168 #define CFG_DRAM_SIZE           0x04000000
 169
 170 #define CFG_FLASH_BASE          PHYS_FLASH_1
 171
 172 #define FPGA_REGS_BASE_PHYSICAL 0x08000000
 173
 174 /*
 175  * GPIO settings
 176  */
 177 #define CFG_GPSR0_VAL           0x00008000
 178 #define CFG_GPSR1_VAL           0x00FC0382
 179 #define CFG_GPSR2_VAL           0x0001FFFF
 180 #define CFG_GPCR0_VAL           0x00000000
 181 #define CFG_GPCR1_VAL           0x00000000
 182 #define CFG_GPCR2_VAL           0x00000000
 183 #define CFG_GPDR0_VAL           0x0060A800
 184 #define CFG_GPDR1_VAL           0x00FF0382
 185 #define CFG_GPDR2_VAL           0x0001C000
 186 #define CFG_GAFR0_L_VAL         0x98400000
 187 #define CFG_GAFR0_U_VAL         0x00002950
 188 #define CFG_GAFR1_L_VAL         0x000A9558
 189 #define CFG_GAFR1_U_VAL         0x0005AAAA
 190 #define CFG_GAFR2_L_VAL         0xA0000000
 191 #define CFG_GAFR2_U_VAL         0x00000002
 192
 193 #define CFG_PSSR_VAL            0x20
 194
 195 /*
 196  * Memory settings
 197  */
 198 #define CFG_MSC0_VAL            0x23F223F2
 199 #define CFG_MSC1_VAL            0x3FF1A441
 200 #define CFG_MSC2_VAL            0x7FF97FF1
 201 #define CFG_MDCNFG_VAL          0x00001AC9
 202 #define CFG_MDREFR_VAL          0x00018018
 203 #define CFG_MDMRS_VAL           0x00000000
 204
 205 /*
 206  * PCMCIA and CF Interfaces
 207  */
 208 #define CFG_MECR_VAL            0x00000000
 209 #define CFG_MCMEM0_VAL          0x00010504
 210 #define CFG_MCMEM1_VAL          0x00010504
 211 #define CFG_MCATT0_VAL          0x00010504
 212 #define CFG_MCATT1_VAL          0x00010504
 213 #define CFG_MCIO0_VAL           0x00004715
 214 #define CFG_MCIO1_VAL           0x00004715
 215
 216 #define _LED                    0x08000010
 217 #define LED_BLANK               0x08000040
 218
 219 /*
 220  * FLASH and environment organization
 221  */
 222 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 223 #define CFG_MAX_FLASH_SECT      128  /* max number of sectors on one chip    */
 224
 225 /* timeout values are in ticks */
 226 #define CFG_FLASH_ERASE_TOUT    (25*CFG_HZ) /* Timeout for Flash Erase */
 227 #define CFG_FLASH_WRITE_TOUT    (25*CFG_HZ) /* Timeout for Flash Write */
 228
 229 /* NOTE: many default partitioning schemes assume the kernel starts at the
 230  * second sector, not an environment.  You have been warned!
 231  */
 232 #define CFG_MONITOR_LEN         PHYS_FLASH_SECT_SIZE
 233 #define CFG_ENV_IS_IN_FLASH     1
 234 #define CFG_ENV_ADDR            (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE)
 235 #define CFG_ENV_SECT_SIZE       PHYS_FLASH_SECT_SIZE
 236 #define CFG_ENV_SIZE            (PHYS_FLASH_SECT_SIZE / 16)
 237
 238
 239 /*
 240  * FPGA Offsets
 241  */
 242 #define WHOAMI_OFFSET           0x00
 243 #define HEXLED_OFFSET           0x10
 244 #define BLANKLED_OFFSET         0x40
 245 #define DISCRETELED_OFFSET      0x40
 246 #define CNFG_SWITCHES_OFFSET    0x50
 247 #define USER_SWITCHES_OFFSET    0x60
 248 #define MISC_WR_OFFSET          0x80
 249 #define MISC_RD_OFFSET          0x90
 250 #define INT_MASK_OFFSET         0xC0
 251 #define INT_CLEAR_OFFSET        0xD0
 252 #define GP_OFFSET               0x100
 253
 254 #endif  /* __CONFIG_H */