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rename CFG_ macros to CONFIG_SYS
[people/ms/u-boot.git] / include / configs / lwmon5.h
1 /*
2 * (C) Copyright 2007-2008
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21 /************************************************************************
22 * lwmon5.h - configuration for lwmon5 board
23 ***********************************************************************/
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*-----------------------------------------------------------------------
28 * High Level Configuration Options
29 *----------------------------------------------------------------------*/
30 #define CONFIG_LWMON5 1 /* Board is lwmon5 */
31 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
32 #define CONFIG_440 1 /* ... PPC440 family */
33 #define CONFIG_4xx 1 /* ... PPC4xx family */
34 #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
35
36 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
37 #define CONFIG_BOARD_POSTCLK_INIT 1 /* Call board_postclk_init */
38 #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
39 #define CONFIG_BOARD_RESET 1 /* Call board_reset */
40
41 /*-----------------------------------------------------------------------
42 * Base addresses -- Note these are effective addresses where the
43 * actual resources get mapped (not physical addresses)
44 *----------------------------------------------------------------------*/
45 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
46 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc() */
47
48 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
49 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
50 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
51 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
52 #define CONFIG_SYS_LIME_BASE_0 0xc0000000
53 #define CONFIG_SYS_LIME_BASE_1 0xc1000000
54 #define CONFIG_SYS_LIME_BASE_2 0xc2000000
55 #define CONFIG_SYS_LIME_BASE_3 0xc3000000
56 #define CONFIG_SYS_FPGA_BASE_0 0xc4000000
57 #define CONFIG_SYS_FPGA_BASE_1 0xc4200000
58 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
59 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
60 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
61 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
62 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
63 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
64
65 /* Don't change either of these */
66 #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */
67
68 #define CONFIG_SYS_USB2D0_BASE 0xe0000100
69 #define CONFIG_SYS_USB_DEVICE 0xe0000000
70 #define CONFIG_SYS_USB_HOST 0xe0000400
71
72 /*-----------------------------------------------------------------------
73 * Initial RAM & stack pointer
74 *----------------------------------------------------------------------*/
75 /*
76 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
77 * the POST_WORD from OCM to a 440EPx register that preserves it's
78 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
79 * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
80 */
81 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
82 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
83 #define CONFIG_SYS_INIT_RAM_END (4 << 10)
84 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/
85 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
86 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
87 #define CONFIG_SYS_POST_ALT_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
88 /* unused GPT0 COMP reg */
89 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
90 /* 440EPx errata CHIP 11 */
91 #define CONFIG_SYS_OCM_SIZE (16 << 10)
92
93 /* Additional registers for watchdog timer post test */
94
95 #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
96 #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
97 #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
98 #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
99 #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
100 #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
101 #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
102 #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
103 #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
104 #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
105
106 /*-----------------------------------------------------------------------
107 * Serial Port
108 *----------------------------------------------------------------------*/
109 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
110 #define CONFIG_BAUDRATE 115200
111 #define CONFIG_SERIAL_MULTI 1
112 /* define this if you want console on UART1 */
113 #define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */
114
115 #define CONFIG_SYS_BAUDRATE_TABLE \
116 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
117
118 /*-----------------------------------------------------------------------
119 * Environment
120 *----------------------------------------------------------------------*/
121 #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
122
123 /*-----------------------------------------------------------------------
124 * FLASH related
125 *----------------------------------------------------------------------*/
126 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
127 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
128
129 #define CONFIG_SYS_FLASH0 0xFC000000
130 #define CONFIG_SYS_FLASH1 0xF8000000
131 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
132
133 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
134 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
135
136 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
137 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
138
139 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
140 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
141
142 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
143 #define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
144
145 #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
146 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
147 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
148
149 /* Address and size of Redundant Environment Sector */
150 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
151 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
152
153 /*-----------------------------------------------------------------------
154 * DDR SDRAM
155 *----------------------------------------------------------------------*/
156 #define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */
157 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
158 #define CONFIG_DDR_DATA_EYE 1 /* use DDR2 optimization */
159 #define CONFIG_DDR_ECC 1 /* enable ECC */
160 #define CONFIG_SYS_POST_ECC_ON CONFIG_SYS_POST_ECC
161
162 /* POST support */
163 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
164 CONFIG_SYS_POST_CPU | \
165 CONFIG_SYS_POST_ECC_ON | \
166 CONFIG_SYS_POST_ETHER | \
167 CONFIG_SYS_POST_FPU | \
168 CONFIG_SYS_POST_I2C | \
169 CONFIG_SYS_POST_MEMORY | \
170 CONFIG_SYS_POST_OCM | \
171 CONFIG_SYS_POST_RTC | \
172 CONFIG_SYS_POST_SPR | \
173 CONFIG_SYS_POST_UART | \
174 CONFIG_SYS_POST_SYSMON | \
175 CONFIG_SYS_POST_WATCHDOG | \
176 CONFIG_SYS_POST_DSP | \
177 CONFIG_SYS_POST_BSPEC1 | \
178 CONFIG_SYS_POST_BSPEC2 | \
179 CONFIG_SYS_POST_BSPEC3 | \
180 CONFIG_SYS_POST_BSPEC4 | \
181 CONFIG_SYS_POST_BSPEC5)
182
183 #define CONFIG_POST_WATCHDOG {\
184 "Watchdog timer test", \
185 "watchdog", \
186 "This test checks the watchdog timer.", \
187 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
188 &lwmon5_watchdog_post_test, \
189 NULL, \
190 NULL, \
191 CONFIG_SYS_POST_WATCHDOG \
192 }
193
194 #define CONFIG_POST_BSPEC1 {\
195 "dsPIC init test", \
196 "dspic_init", \
197 "This test returns result of dsPIC READY test run earlier.", \
198 POST_RAM | POST_ALWAYS, \
199 &dspic_init_post_test, \
200 NULL, \
201 NULL, \
202 CONFIG_SYS_POST_BSPEC1 \
203 }
204
205 #define CONFIG_POST_BSPEC2 {\
206 "dsPIC test", \
207 "dspic", \
208 "This test gets result of dsPIC POST and dsPIC version.", \
209 POST_RAM | POST_ALWAYS, \
210 &dspic_post_test, \
211 NULL, \
212 NULL, \
213 CONFIG_SYS_POST_BSPEC2 \
214 }
215
216 #define CONFIG_POST_BSPEC3 {\
217 "FPGA test", \
218 "fpga", \
219 "This test checks FPGA registers and memory.", \
220 POST_RAM | POST_ALWAYS, \
221 &fpga_post_test, \
222 NULL, \
223 NULL, \
224 CONFIG_SYS_POST_BSPEC3 \
225 }
226
227 #define CONFIG_POST_BSPEC4 {\
228 "GDC test", \
229 "gdc", \
230 "This test checks GDC registers and memory.", \
231 POST_RAM | POST_ALWAYS, \
232 &gdc_post_test, \
233 NULL, \
234 NULL, \
235 CONFIG_SYS_POST_BSPEC4 \
236 }
237
238 #define CONFIG_POST_BSPEC5 {\
239 "SYSMON1 test", \
240 "sysmon1", \
241 "This test checks GPIO_62_EPX pin indicating power failure.", \
242 POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
243 &sysmon1_post_test, \
244 NULL, \
245 NULL, \
246 CONFIG_SYS_POST_BSPEC5 \
247 }
248
249 #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
250 #define CONFIG_LOGBUFFER
251 /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
252 #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
253 #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
254 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
255
256 /*-----------------------------------------------------------------------
257 * I2C
258 *----------------------------------------------------------------------*/
259 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
260 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
261 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
262 #define CONFIG_SYS_I2C_SLAVE 0x7F
263
264 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM AT24C128 */
265 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
266 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
267 /* 64 byte page write mode using*/
268 /* last 6 bits of the address */
269 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
270
271 #define CONFIG_RTC_PCF8563 1 /* enable Philips PCF8563 RTC */
272 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
273 #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
274 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
275
276 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
277 #if 0
278 #define CONFIG_AUTOBOOT_KEYED /* Enable "password" protection */
279 #define CONFIG_AUTOBOOT_PROMPT \
280 "\nEnter password - autoboot in %d sec...\n", bootdelay
281 #define CONFIG_AUTOBOOT_DELAY_STR " " /* "password" */
282 #endif
283
284 #define CONFIG_PREBOOT "setenv bootdelay 15"
285
286 #undef CONFIG_BOOTARGS
287
288 #define CONFIG_EXTRA_ENV_SETTINGS \
289 "hostname=lwmon5\0" \
290 "netdev=eth0\0" \
291 "unlock=yes\0" \
292 "logversion=2\0" \
293 "nfsargs=setenv bootargs root=/dev/nfs rw " \
294 "nfsroot=${serverip}:${rootpath}\0" \
295 "ramargs=setenv bootargs root=/dev/ram rw\0" \
296 "addip=setenv bootargs ${bootargs} " \
297 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
298 ":${hostname}:${netdev}:off panic=1\0" \
299 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
300 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
301 "flash_nfs=run nfsargs addip addtty addmisc;" \
302 "bootm ${kernel_addr}\0" \
303 "flash_self=run ramargs addip addtty addmisc;" \
304 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
305 "net_nfs=tftp 200000 ${bootfile};" \
306 "run nfsargs addip addtty addmisc;bootm\0" \
307 "rootpath=/opt/eldk/ppc_4xxFP\0" \
308 "bootfile=/tftpboot/lwmon5/uImage\0" \
309 "kernel_addr=FC000000\0" \
310 "ramdisk_addr=FC180000\0" \
311 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
312 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
313 "cp.b 200000 FFF80000 80000\0" \
314 "upd=run load update\0" \
315 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
316 "autoscr 200000\0" \
317 ""
318 #define CONFIG_BOOTCOMMAND "run flash_self"
319
320 #if 0
321 #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
322 #else
323 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
324 #endif
325
326 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
327 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
328
329 #define CONFIG_IBM_EMAC4_V4 1
330 #define CONFIG_MII 1 /* MII PHY management */
331 #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
332
333 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
334 #define CONFIG_PHY_RESET_DELAY 300
335
336 #define CONFIG_HAS_ETH0
337 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
338
339 #define CONFIG_NET_MULTI 1
340 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
341 #define CONFIG_PHY1_ADDR 1
342
343 /* Video console */
344 #define CONFIG_VIDEO
345 #define CONFIG_VIDEO_MB862xx
346 #define CONFIG_CFB_CONSOLE
347 #define CONFIG_VIDEO_LOGO
348 #define CONFIG_CONSOLE_EXTRA_INFO
349 #define VIDEO_FB_16BPP_PIXEL_SWAP
350
351 #define CONFIG_VGA_AS_SINGLE_DEVICE
352 #define CONFIG_VIDEO_SW_CURSOR
353 #define CONFIG_SPLASH_SCREEN
354
355 /* USB */
356 #ifdef CONFIG_440EPX
357 #define CONFIG_USB_OHCI
358 #define CONFIG_USB_STORAGE
359
360 /* Comment this out to enable USB 1.1 device */
361 #define USB_2_0_DEVICE
362
363 #endif /* CONFIG_440EPX */
364
365 /* Partitions */
366 #define CONFIG_MAC_PARTITION
367 #define CONFIG_DOS_PARTITION
368 #define CONFIG_ISO_PARTITION
369
370 /*
371 * BOOTP options
372 */
373 #define CONFIG_BOOTP_BOOTFILESIZE
374 #define CONFIG_BOOTP_BOOTPATH
375 #define CONFIG_BOOTP_GATEWAY
376 #define CONFIG_BOOTP_HOSTNAME
377
378 /*
379 * Command line configuration.
380 */
381 #include <config_cmd_default.h>
382
383 #define CONFIG_CMD_ASKENV
384 #define CONFIG_CMD_DATE
385 #define CONFIG_CMD_DHCP
386 #define CONFIG_CMD_DIAG
387 #define CONFIG_CMD_EEPROM
388 #define CONFIG_CMD_ELF
389 #define CONFIG_CMD_FAT
390 #define CONFIG_CMD_I2C
391 #define CONFIG_CMD_IRQ
392 #define CONFIG_CMD_LOG
393 #define CONFIG_CMD_MII
394 #define CONFIG_CMD_NET
395 #define CONFIG_CMD_NFS
396 #define CONFIG_CMD_PCI
397 #define CONFIG_CMD_PING
398 #define CONFIG_CMD_REGINFO
399 #define CONFIG_CMD_SDRAM
400
401 #ifdef CONFIG_VIDEO
402 #define CONFIG_CMD_BMP
403 #endif
404
405 #ifdef CONFIG_440EPX
406 #define CONFIG_CMD_USB
407 #endif
408
409 /*-----------------------------------------------------------------------
410 * Miscellaneous configurable options
411 *----------------------------------------------------------------------*/
412 #define CONFIG_SUPPORT_VFAT
413
414 #define CONFIG_SYS_LONGHELP /* undef to save memory */
415 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
416
417 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
418 #ifdef CONFIG_SYS_HUSH_PARSER
419 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
420 #endif
421
422 #if defined(CONFIG_CMD_KGDB)
423 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
424 #else
425 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
426 #endif
427 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
428 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
429 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
430
431 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
432 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
433
434 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
435 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
436
437 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
438
439 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
440 #define CONFIG_LOOPW 1 /* enable loopw command */
441 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
442 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
443
444 /*-----------------------------------------------------------------------
445 * PCI stuff
446 *----------------------------------------------------------------------*/
447 /* General PCI */
448 #define CONFIG_PCI /* include pci support */
449 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
450 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
451 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
452
453 /* Board-specific PCI */
454 #define CONFIG_SYS_PCI_TARGET_INIT
455 #define CONFIG_SYS_PCI_MASTER_INIT
456
457 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
458 #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
459
460 #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
461 #define CONFIG_WD_PERIOD 40000 /* in usec */
462 #define CONFIG_WD_MAX_RATE 66600 /* in ticks */
463
464 /*
465 * For booting Linux, the board info and command line data
466 * have to be in the first 8 MB of memory, since this is
467 * the maximum mapped by the Linux kernel during initialization.
468 */
469 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
470
471 /*-----------------------------------------------------------------------
472 * External Bus Controller (EBC) Setup
473 *----------------------------------------------------------------------*/
474 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
475
476 /* Memory Bank 0 (NOR-FLASH) initialization */
477 #define CONFIG_SYS_EBC_PB0AP 0x03050200
478 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
479
480 /* Memory Bank 1 (Lime) initialization */
481 #define CONFIG_SYS_EBC_PB1AP 0x01004380
482 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xdc000)
483
484 /* Memory Bank 2 (FPGA) initialization */
485 #define CONFIG_SYS_EBC_PB2AP 0x01004400
486 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
487
488 /* Memory Bank 3 (FPGA2) initialization */
489 #define CONFIG_SYS_EBC_PB3AP 0x01004400
490 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
491
492 #define CONFIG_SYS_EBC_CFG 0xb8400000
493
494 /*-----------------------------------------------------------------------
495 * Graphics (Fujitsu Lime)
496 *----------------------------------------------------------------------*/
497 /* SDRAM Clock frequency adjustment register */
498 #define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
499 /* Lime Clock frequency is to set 100MHz */
500 #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
501 #if 0
502 /* Lime Clock frequency for 133MHz */
503 #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
504 #endif
505
506 /* SDRAM Parameter register */
507 #define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
508 /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
509 and pixel flare on display when 133MHz was configured. According to
510 SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
511 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
512 #define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F3
513 #else
514 #define CONFIG_SYS_LIME_MMR_VALUE 0x414FB7F2
515 #endif
516
517 /*-----------------------------------------------------------------------
518 * GPIO Setup
519 *----------------------------------------------------------------------*/
520 #define CONFIG_SYS_GPIO_PHY1_RST 12
521 #define CONFIG_SYS_GPIO_FLASH_WP 14
522 #define CONFIG_SYS_GPIO_PHY0_RST 22
523 #define CONFIG_SYS_GPIO_DSPIC_READY 51
524 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
525 #define CONFIG_SYS_GPIO_HIGHSIDE 56
526 #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
527 #define CONFIG_SYS_GPIO_BOARD_RESET 58
528 #define CONFIG_SYS_GPIO_LIME_S 59
529 #define CONFIG_SYS_GPIO_LIME_RST 60
530 #define CONFIG_SYS_GPIO_SYSMON_STATUS 62
531 #define CONFIG_SYS_GPIO_WATCHDOG 63
532
533 /*-----------------------------------------------------------------------
534 * PPC440 GPIO Configuration
535 */
536 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
537 { \
538 /* GPIO Core 0 */ \
539 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
540 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
541 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
542 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
543 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
544 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
545 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
546 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
547 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
548 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
549 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
550 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
551 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
552 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
553 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
554 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
555 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
556 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
557 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
558 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
559 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
560 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
561 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
562 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
563 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
564 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
565 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
566 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
567 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
568 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
569 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
570 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
571 }, \
572 { \
573 /* GPIO Core 1 */ \
574 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
575 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
576 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
577 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
578 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
579 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
580 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
581 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
582 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
583 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
584 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
585 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
586 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
587 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
588 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
589 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
590 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
591 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
592 {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
593 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
594 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
595 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
596 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
597 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
598 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
599 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
600 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
601 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
602 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
603 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
604 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
605 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
606 } \
607 }
608
609 /*
610 * Internal Definitions
611 *
612 * Boot Flags
613 */
614 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
615 #define BOOTFLAG_WARM 0x02 /* Software reboot */
616
617 #if defined(CONFIG_CMD_KGDB)
618 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
619 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
620 #endif
621 #endif /* __CONFIG_H */
"Das U-Boot" Source Tree