include/configs/manroland/mpc5200-common.h

   1 /*
   2  * (C) Copyright 2009
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __MANROLAND_MPC52XX__COMMON_H
   9 #define __MANROLAND_MPC52XX__COMMON_H
  10
  11 /*
  12  * High Level Configuration Options
  13  * (easy to change)
  14  */
  15 #define CONFIG_MPC5200          1       /* MPC5200 CPU */
  16
  17 /* ... running at 33.000000MHz  */
  18 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000
  19
  20 #define CONFIG_HIGH_BATS        1       /* High BATs supported          */
  21
  22 /*
  23  * Serial console configuration
  24  */
  25 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  26 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200,\
  27                                          230400 }
  28
  29 #if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
  30 #   define CONFIG_SYS_LOWBOOT           1
  31 #endif
  32
  33 /*
  34  * IPB Bus clocking configuration.
  35  */
  36 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
  37
  38 /*
  39  * Flash configuration
  40  */
  41 #define CONFIG_SYS_FLASH_BASE           0xFF800000
  42
  43 #define CONFIG_SYS_FLASH_SIZE           0x00800000 /* 8 MByte */
  44
  45 #define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
  46 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
  47                                            (= chip selects) */
  48 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout [ms]*/
  49 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout [ms]*/
  50
  51 #define CONFIG_FLASH_CFI_DRIVER
  52 #define CONFIG_SYS_FLASH_CFI
  53 #define CONFIG_SYS_FLASH_EMPTY_INFO
  54 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
  55
  56 /*
  57  * Environment settings
  58  */
  59 #define CONFIG_ENV_IS_IN_FLASH  1
  60 #define CONFIG_ENV_SIZE         0x4000
  61 #define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
  62 #define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
  63
  64 /*
  65  * Memory map
  66  */
  67 #define CONFIG_SYS_MBAR         0xF0000000
  68 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
  69
  70 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE -\
  71                                          GENERATED_GBL_DATA_SIZE)
  72 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  73
  74 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  75 #define CONFIG_SYS_SRAM_BASE    0x80100000      /* CS 1 */
  76 #define CONFIG_SYS_DISPLAY_BASE 0x80600000      /* CS 3 */
  77
  78 /* Settings for XLB = 132 MHz */
  79 #define SDRAM_DDR        1
  80 #define SDRAM_MODE      0x018D0000
  81 #define SDRAM_EMODE     0x40090000
  82 #define SDRAM_CONTROL   0x714f0f00
  83 #define SDRAM_CONFIG1   0x73722930
  84 #define SDRAM_CONFIG2   0x47770000
  85 #define SDRAM_TAPDELAY  0x10000000
  86
  87 /* Use ON-Chip SRAM until RAM will be available */
  88 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
  89 #ifdef CONFIG_POST
  90 /* preserve space for the post_word at end of on-chip SRAM */
  91 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
  92 #else
  93 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
  94 #endif
  95
  96 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
  97 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  98 #   define CONFIG_SYS_RAMBOOT           1
  99 #endif
 100
 101 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)
 102 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 103 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 104
 105 /*
 106  * Ethernet configuration
 107  */
 108 #define CONFIG_MPC5xxx_FEC      1
 109 #define CONFIG_MPC5xxx_FEC_MII100
 110 #define CONFIG_PHY_ADDR         0x00
 111 #define CONFIG_MII              1
 112
 113 /*use  Hardware WDT */
 114 #define CONFIG_HW_WATCHDOG
 115
 116 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs     */
 117 #if defined(CONFIG_CMD_KGDB)
 118 #  define CONFIG_SYS_CACHELINE_SHIFT    5 /* log base 2 of the above value */
 119 #endif
 120
 121 /*
 122  * Various low-level settings
 123  */
 124 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 125 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 126
 127 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 128 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 129 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 130 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 131
 132 /* 8Mbit SRAM @0x80100000 */
 133 #define CONFIG_SYS_CS1_START            CONFIG_SYS_SRAM_BASE
 134
 135 #define CONFIG_SYS_CS_BURST             0x00000000
 136 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 137
 138 /*-----------------------------------------------------------------------
 139  * IDE/ATA stuff Supports IDE harddisk
 140  *-----------------------------------------------------------------------
 141  */
 142
 143 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 144
 145 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus       */
 146
 147 #define CONFIG_IDE_PREINIT      1
 148
 149 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 150
 151 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 152
 153 /* Offset for data I/O                  */
 154 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 155
 156 /* Offset for normal register accesses  */
 157 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 158
 159 /* Offset for alternate registers       */
 160 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 161
 162 /* Interval between registers   */
 163 #define CONFIG_SYS_ATA_STRIDE          4
 164
 165 #define CONFIG_ATAPI            1
 166
 167 #define OF_CPU                  "PowerPC,5200@0"
 168 #define OF_SOC                  "soc5200@f0000000"
 169 #define OF_TBCLK                (bd->bi_busfreq / 4)
 170 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
 171 #define CONFIG_OF_IDE_FIXUP
 172
 173 #endif /* __MANROLAND_MPC52XX__COMMON_H */