include/configs/mcc200.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5200
  33 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  34 #define CONFIG_MCC200           1       /* ... on MCC200 board                  */
  35
  36 /*
  37  * Valid values for CONFIG_SYS_TEXT_BASE are:
  38  * 0xFC000000   boot low (standard configuration)
  39  * 0xFFF00000   boot high
  40  * 0x00100000   boot from RAM (for testing only)
  41  */
  42 #ifndef CONFIG_SYS_TEXT_BASE
  43 #define CONFIG_SYS_TEXT_BASE    0xFC000000
  44 #endif
  45
  46 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33MHz                */
  47
  48 #define CONFIG_MISC_INIT_R
  49
  50 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  51
  52 /*
  53  * Serial console configuration
  54  *
  55  *  To select console on the one of 8 external UARTs,
  56  * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
  57  * or as 5, 6, 7, or 8 for the second Quad UART.
  58  * COM11, COM12, COM13, COM14 are located on the second Quad UART.
  59  *
  60  *  CONFIG_PSC_CONSOLE must be undefined in this case.
  61  */
  62 #if !defined(CONFIG_PRS200)
  63 /* MCC200 configuration: */
  64 #ifdef CONFIG_CONSOLE_COM12
  65 #define CONFIG_QUART_CONSOLE    6       /* console is on UARTF of QUART2        */
  66 #else
  67 #define CONFIG_QUART_CONSOLE    8       /* console is on UARTH of QUART2        */
  68 #endif
  69 #else
  70 /* PRS200 configuration: */
  71 #undef CONFIG_QUART_CONSOLE
  72 #endif /* CONFIG_PRS200 */
  73 /*
  74  *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
  75  * and undefine CONFIG_QUART_CONSOLE.
  76  */
  77 #if !defined(CONFIG_PRS200)
  78 /* MCC200 configuration: */
  79 #define CONFIG_SERIAL_MULTI     1
  80 #define CONFIG_PSC_CONSOLE      1       /* PSC1 may be COM */
  81 #define CONFIG_PSC_CONSOLE2     2       /* PSC2 is PSoC */
  82 #else
  83 /* PRS200 configuration: */
  84 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1           */
  85 #endif
  86 #if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
  87         !defined(CONFIG_SERIAL_MULTI)
  88 #error "Select only one console device!"
  89 #endif
  90 #define CONFIG_BAUDRATE         115200
  91 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  92
  93 #define CONFIG_MII              1
  94
  95 #define CONFIG_DOS_PARTITION
  96
  97 /* USB */
  98 #define CONFIG_USB_OHCI
  99 #define CONFIG_USB_STORAGE
 100 /* automatic software updates (see board/mcc200/auto_update.c) */
 101 #define CONFIG_AUTO_UPDATE 1
 102
 103
 104 /*
 105  * BOOTP options
 106  */
 107 #define CONFIG_BOOTP_BOOTFILESIZE
 108 #define CONFIG_BOOTP_BOOTPATH
 109 #define CONFIG_BOOTP_GATEWAY
 110 #define CONFIG_BOOTP_HOSTNAME
 111
 112
 113 /*
 114  * Command line configuration.
 115  */
 116 #include <config_cmd_default.h>
 117
 118 #define CONFIG_CMD_BEDBUG
 119 #define CONFIG_CMD_FAT
 120 #define CONFIG_CMD_I2C
 121 #define CONFIG_CMD_USB
 122
 123 #undef  CONFIG_CMD_NET
 124 #undef  CONFIG_CMD_NFS
 125
 126 /*
 127  * Autobooting
 128  */
 129 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 130
 131 #define CONFIG_PREBOOT  "echo;" \
 132         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 133         "echo"
 134
 135 #undef  CONFIG_BOOTARGS
 136
 137 #define XMK_STR(x)              #x
 138 #define MK_STR(x)               XMK_STR(x)
 139
 140 #ifdef CONFIG_PRS200
 141 # define CONFIG_SYS__BOARDNAME          "prs200"
 142 # define CONFIG_SYS__LINUX_CONSOLE      "ttyS0"
 143 #else
 144 # define CONFIG_SYS__BOARDNAME          "mcc200"
 145 # define CONFIG_SYS__LINUX_CONSOLE      "ttyEU5"
 146 #endif
 147
 148 /* Network */
 149 #define CONFIG_ETHADDR  00:17:17:ff:00:00
 150 #define CONFIG_IPADDR   10.76.9.29
 151 #define CONFIG_SERVERIP 10.76.9.1
 152
 153 #include <version.h> /* For U-Boot version */
 154
 155 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 156         "ubootver=" U_BOOT_VERSION "\0"                                 \
 157         "netdev=eth0\0"                                                 \
 158         "hostname=" CONFIG_SYS__BOARDNAME "\0"                                  \
 159         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 160                 "nfsroot=${serverip}:${rootpath}\0"                     \
 161         "ramargs=setenv bootargs root=/dev/mtdblock2 "                  \
 162                 "rootfstype=cramfs\0"                                   \
 163         "addip=setenv bootargs ${bootargs} "                            \
 164                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 165                 ":${hostname}:${netdev}:off panic=1\0"                  \
 166         "addcons=setenv bootargs ${bootargs} "                          \
 167                 "console=${console},${baudrate} "                       \
 168                 "ubootver=${ubootver} board=${board}\0"                 \
 169         "flash_nfs=run nfsargs addip addcons;"                          \
 170                 "bootm ${kernel_addr}\0"                                \
 171         "flash_self=run ramargs addip addcons;"                         \
 172                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 173         "net_nfs=tftp 200000 ${bootfile};"                              \
 174                 "run nfsargs addip addcons;bootm\0"                     \
 175         "console=" CONFIG_SYS__LINUX_CONSOLE "\0"                               \
 176         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 177         "bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0"         \
 178         "load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0"     \
 179         "text_base=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"                          \
 180         "kernel_addr=0xFC0C0000\0"                                      \
 181         "update=protect off ${text_base} +${filesize};"                 \
 182                 "era ${text_base} +${filesize};"                        \
 183                 "cp.b 200000 ${text_base} ${filesize}\0"                \
 184         "unlock=yes\0"                                                  \
 185         ""
 186 #undef MK_STR
 187 #undef XMK_STR
 188
 189 #define CONFIG_BOOTCOMMAND      "run flash_self"
 190
 191 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
 192 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 193
 194 /*
 195  * IPB Bus clocking configuration.
 196  */
 197 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 198
 199 /*
 200  * I2C configuration
 201  */
 202 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 203 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 204
 205 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 206 #define CONFIG_SYS_I2C_SLAVE            0x7F
 207
 208 /*
 209  * Flash configuration (8,16 or 32 MB)
 210  * TEXT base always at 0xFFF00000
 211  * ENV_ADDR always at  0xFFF40000
 212  * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
 213  *               0xFE000000 for 32 MB
 214  *               0xFF000000 for 16 MB
 215  *               0xFF800000 for  8 MB
 216  */
 217 #define CONFIG_SYS_FLASH_BASE           0xfc000000
 218 #define CONFIG_SYS_FLASH_SIZE           0x04000000
 219
 220 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 221 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 222
 223 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 224
 225 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 226 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 227
 228 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 229 #define CONFIG_SYS_FLASH_PROTECTION     1       /* hardware flash protection            */
 230
 231 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 232 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 233
 234 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 235 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 236
 237 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars       */
 238
 239 #define CONFIG_ENV_SECT_SIZE    0x40000 /* size of one complete sector  */
 240 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 241 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 242
 243 /* Address and size of Redundant Environment Sector     */
 244 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 245 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 246
 247 #define CONFIG_ENV_OVERWRITE    1       /* allow modification of vendor params */
 248
 249 #if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE
 250 #define CONFIG_SYS_LOWBOOT      1
 251 #endif
 252
 253 /*
 254  * Memory map
 255  */
 256 #define CONFIG_SYS_MBAR         0xf0000000
 257 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 258 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 259
 260 /* Use SRAM until RAM will be available */
 261 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 262 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 263
 264
 265 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 266 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 267
 268 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 269 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 270 #   define CONFIG_SYS_RAMBOOT           1
 271 #endif
 272
 273 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 274 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 512 kB for malloc()  */
 275 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 276
 277 /*
 278  * Ethernet configuration
 279  */
 280 /* #define CONFIG_MPC5xxx_FEC   1 */
 281 /* #define CONFIG_MPC5xxx_FEC_MII100 */
 282 /*
 283  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 284  */
 285 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 286 #define CONFIG_PHY_ADDR         1
 287
 288 /*
 289  * LCD Splash Screen
 290  */
 291 #if !defined(CONFIG_PRS200)
 292 #define CONFIG_LCD              1
 293 #define CONFIG_PROGRESSBAR 1
 294 #endif
 295
 296 #if defined(CONFIG_LCD)
 297 #define CONFIG_SPLASH_SCREEN    1
 298 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 299 #define LCD_BPP                 LCD_MONOCHROME
 300 #endif
 301
 302 /*
 303  * GPIO configuration
 304  */
 305 /* 0x10000004 = 32MB SDRAM */
 306 /* 0x90000004 = 64MB SDRAM */
 307 #if defined(CONFIG_LCD)
 308 /* set PSC2 in UART mode */
 309 #define CONFIG_SYS_GPS_PORT_CONFIG      0x00000044
 310 #else
 311 #define CONFIG_SYS_GPS_PORT_CONFIG      0x00000004
 312 #endif
 313
 314 /*
 315  * Miscellaneous configurable options
 316  */
 317 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 318 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 319 #if defined(CONFIG_CMD_KGDB)
 320 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 321 #else
 322 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 323 #endif
 324 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size    */
 325 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 326 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 327
 328 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 329 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 330
 331 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 332
 333 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 334
 335 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 336 #if defined(CONFIG_CMD_KGDB)
 337 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 338 #endif
 339
 340 /*
 341  * Various low-level settings
 342  */
 343 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 344 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 345
 346 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 347 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 348 #define CONFIG_SYS_BOOTCS_CFG           0x0004fb00
 349 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 350 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 351
 352 /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 353 #define CONFIG_SYS_CS2_START            0x80000000
 354 #define CONFIG_SYS_CS2_SIZE             0x00001000
 355 #define CONFIG_SYS_CS2_CFG              0x1d300
 356
 357 /* Second Quad UART @0x80010000 */
 358 #define CONFIG_SYS_CS1_START            0x80010000
 359 #define CONFIG_SYS_CS1_SIZE             0x00001000
 360 #define CONFIG_SYS_CS1_CFG              0x1d300
 361
 362 /* Leica - build revision resistors */
 363 /*
 364 #define CONFIG_SYS_CS3_START            0x80020000
 365 #define CONFIG_SYS_CS3_SIZE             0x00000004
 366 #define CONFIG_SYS_CS3_CFG              0x1d300
 367 */
 368
 369 /*
 370  *  Select one of quarts as a default
 371  * console. If undefined - PSC console
 372  * wil be default
 373  */
 374 #define CONFIG_SYS_CS_BURST             0x00000000
 375 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 376
 377 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 378
 379 /*
 380  * QUART Expanders support
 381  */
 382 #if defined(CONFIG_QUART_CONSOLE)
 383 /*
 384  * We'll use NS16550 chip routines,
 385  */
 386 #define CONFIG_SYS_NS16550              1
 387 #define CONFIG_SYS_NS16550_SERIAL       1
 388 #define CONFIG_CONS_INDEX       1
 389 /*
 390  *  To achieve necessary offset on SC16C554
 391  * A0-A2 (register select) pins with NS16550
 392  * functions (in struct NS16550), REG_SIZE
 393  * should be 4, because A0-A2 pins are connected
 394  * to DA2-DA4 address bus lines.
 395  */
 396 #define CONFIG_SYS_NS16550_REG_SIZE     4
 397 /*
 398  * LocalPlus Bus already inited in cpu_init_f(),
 399  * so can work with QUART's chip selects.
 400  * One of four SC16C554 UARTs is selected with
 401  * A3-A4 (DA5-DA6) lines.
 402  */
 403 #if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
 404 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
 405 #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
 406 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
 407 #else
 408 #error "Wrong QUART expander number."
 409 #endif
 410
 411 /*
 412  * SC16C554 chip's external crystal oscillator frequency
 413  * is 7.3728 MHz
 414  */
 415 #define CONFIG_SYS_NS16550_CLK          7372800
 416 #endif /* CONFIG_QUART_CONSOLE */
 417 /*-----------------------------------------------------------------------
 418  * USB stuff
 419  *-----------------------------------------------------------------------
 420  */
 421 #define CONFIG_USB_CLOCK        0x0001BBBB
 422 #define CONFIG_USB_CONFIG       0x00005000
 423
 424 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot     */
 425 #define CONFIG_AUTOBOOT_STOP_STR        "432"
 426 #define CONFIG_SILENT_CONSOLE   1
 427
 428 #endif /* __CONFIG_H */