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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/mecp5200.h
2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /*************************************************************************
26 * (c) 2005 esd gmbh Hannover
30 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
32 *************************************************************************/
38 * High Level Configuration Options
42 #define CONFIG_MPC5200 1 /* This is an MPC5xxx CPU */
43 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
44 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
45 #define CONFIG_MECP5200 1 /* ... on MECP5200 board */
46 #define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
48 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
50 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
51 #define BOOTFLAG_WARM 0x02 /* Software reboot */
53 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
56 * Serial console configuration
58 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
60 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
62 #define CONFIG_BAUDRATE 9600 /* ... at 115200 bps */
64 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
67 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
70 #if 0 /* test-only !!! */
71 #define CONFIG_NET_MULTI 1
72 #define CONFIG_EEPRO100 1
73 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
74 #define CONFIG_NS8382X 1
82 #define CONFIG_MAC_PARTITION
83 #define CONFIG_DOS_PARTITION
87 #define CONFIG_USB_OHCI
88 #define CONFIG_USB_STORAGE
95 #define CONFIG_BOOTP_BOOTFILESIZE
96 #define CONFIG_BOOTP_BOOTPATH
97 #define CONFIG_BOOTP_GATEWAY
98 #define CONFIG_BOOTP_HOSTNAME
102 * Command line configuration.
104 #include <config_cmd_default.h>
106 #define CONFIG_CMD_EEPROM
107 #define CONFIG_CMD_FAT
108 #define CONFIG_CMD_EXT2
109 #define CONFIG_CMD_I2C
110 #define CONFIG_CMD_IDE
111 #define CONFIG_CMD_BSP
112 #define CONFIG_CMD_ELF
115 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
116 # define CONFIG_SYS_LOWBOOT 1
117 # define CONFIG_SYS_LOWBOOT16 1
119 #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
120 # define CONFIG_SYS_LOWBOOT 1
121 # define CONFIG_SYS_LOWBOOT08 1
127 #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
129 #define CONFIG_PREBOOT "echo;" \
130 "echo Welcome to CBX-CPU5200 (mecp5200);" \
133 #undef CONFIG_BOOTARGS
135 #define CONFIG_EXTRA_ENV_SETTINGS \
137 "flash_vxworks0=run ata_vxworks_args;setenv loadaddr ff000000;bootvx\0" \
138 "flash_vxworks1=run ata_vxworks_args;setenv loadaddr ff200000:bootvx\0" \
139 "net_vxworks=tftp $(loadaddr) $(image);run vxworks_args;bootvx\0" \
140 "vxworks_args=setenv bootargs fec(0,0)$(host):$(image) h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script)\0" \
141 "ata_vxworks_args=setenv bootargs /ata0/vxWorks h=$(serverip) e=$(ipaddr) g=$(gatewayip) u=$(user) $(pass) tn=$(target) s=$(script) o=fec0 \0" \
142 "loadaddr=01000000\0" \
143 "serverip=192.168.2.99\0" \
144 "gatewayip=10.0.0.79\0" \
146 "target=mecp5200.esd\0" \
147 "script=mecp5200.bat\0" \
148 "image=/tftpboot/vxWorks_mecp5200\0" \
149 "ipaddr=10.0.13.196\0" \
150 "netmask=255.255.0.0\0" \
153 #define CONFIG_BOOTCOMMAND "run flash_vxworks0"
155 #if defined(CONFIG_MPC5200)
157 * IPB Bus clocking configuration.
159 #undef CONFIG_SYS_IPBSPEED_133 /* define for 133MHz speed */
164 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
165 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
167 #define CONFIG_SYS_I2C_SPEED 86000 /* 100 kHz */
168 #define CONFIG_SYS_I2C_SLAVE 0x7F
171 * EEPROM configuration
173 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
175 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
177 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1
179 * Flash configuration
181 #define CONFIG_SYS_FLASH_BASE 0xFFC00000
182 #define CONFIG_SYS_FLASH_SIZE 0x00400000
183 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x003E0000)
184 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
185 #define CONFIG_SYS_MAX_FLASH_SECT 512
187 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
188 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
191 * Environment settings
193 #if 1 /* test-only */
194 #define CONFIG_ENV_IS_IN_FLASH 1
195 #define CONFIG_ENV_SIZE 0x10000
196 #define CONFIG_ENV_SECT_SIZE 0x10000
197 #define CONFIG_ENV_OVERWRITE 1
199 #define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
200 #define CONFIG_ENV_OFFSET 0x0000 /* environment starts at the beginning of the EEPROM */
201 #define CONFIG_ENV_SIZE 0x0400 /* 8192 bytes may be used for env vars*/
202 /* total size of a CAT24WC32 is 8192 bytes */
203 #define CONFIG_ENV_OVERWRITE 1
206 #define CONFIG_FLASH_CFI_DRIVER 1 /* Flash is CFI conformant */
207 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
208 #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
210 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
212 #define CONFIG_SYS_FLASH_INCREMENT 0x00400000 /* size of flash bank */
213 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
214 #define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* show if bank is empty */
220 #define CONFIG_SYS_MBAR 0xF0000000
221 #define CONFIG_SYS_SDRAM_BASE 0x00000000
222 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
224 /* Use SRAM until RAM will be available */
225 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
226 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
229 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
230 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
231 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
233 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
234 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
235 # define CONFIG_SYS_RAMBOOT 1
238 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
239 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
240 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
243 * Ethernet configuration
245 #define CONFIG_MPC5xxx_FEC 1
247 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
249 /* #define CONFIG_FEC_10MBIT 1 */
250 #define CONFIG_PHY_ADDR 0x00
251 #define CONFIG_UDP_CHECKSUM 1
257 #define CONFIG_SYS_GPS_PORT_CONFIG 0x01052444
260 * Miscellaneous configurable options
262 #define CONFIG_SYS_LONGHELP /* undef to save memory */
263 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
264 #if defined(CONFIG_CMD_KGDB)
265 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
267 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
269 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
270 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
271 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
273 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
274 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
276 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
278 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
280 #define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
282 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
283 #if defined(CONFIG_CMD_KGDB)
284 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
288 * Various low-level settings
290 #if defined(CONFIG_MPC5200)
291 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
292 #define CONFIG_SYS_HID0_FINAL HID0_ICE
294 #define CONFIG_SYS_HID0_INIT 0
295 #define CONFIG_SYS_HID0_FINAL 0
298 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
299 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
300 #define CONFIG_SYS_BOOTCS_CFG 0x00085d00
302 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
303 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
305 #define CONFIG_SYS_CS1_START 0xfd000000
306 #define CONFIG_SYS_CS1_SIZE 0x00010000
307 #define CONFIG_SYS_CS1_CFG 0x10101410
309 #define CONFIG_SYS_CS_BURST 0x00000000
310 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
312 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
314 /*-----------------------------------------------------------------------
316 *-----------------------------------------------------------------------
318 #define CONFIG_USB_CLOCK 0x0001BBBB
319 #define CONFIG_USB_CONFIG 0x00001000
321 /*-----------------------------------------------------------------------
322 * IDE/ATA stuff Supports IDE harddisk
323 *-----------------------------------------------------------------------
326 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
328 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
329 #undef CONFIG_IDE_LED /* LED for ide not supported */
331 #define CONFIG_IDE_RESET /* reset for ide supported */
332 #define CONFIG_IDE_PREINIT
334 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
335 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
337 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
339 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
341 /* Offset for data I/O */
342 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
344 /* Offset for normal register accesses */
345 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
347 /* Offset for alternate registers */
348 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
350 /* Interval between registers */
351 #define CONFIG_SYS_ATA_STRIDE 4
353 #endif /* __CONFIG_H */