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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/mgcoge.h
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * High Level Configuration Options
32 #define CONFIG_MPC8247 1
33 #define CONFIG_MPC8272_FAMILY 1
34 #define CONFIG_MGCOGE 1
36 #define CONFIG_CPM2 1 /* Has a CPM2 */
38 /* Do boardspecific init */
39 #define CONFIG_BOARD_EARLY_INIT_R 1
42 * Select serial console configuration
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
48 #define CONFIG_CONS_ON_SMC /* Console is on SMC */
49 #undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50 #undef CONFIG_CONS_NONE /* It's not on external UART */
51 #define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */
54 * Select ethernet configuration
56 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
57 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
60 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
61 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
64 #define CONFIG_ETHER_ON_SCC /* Ethernet is on SCC */
65 #undef CONFIG_ETHER_ON_FCC /* Ethernet is not on FCC */
66 #undef CONFIG_ETHER_NONE /* No external Ethernet */
68 #define CONFIG_ETHER_INDEX 4
69 #define CONFIG_SYS_SCC_TOUT_LOOP 10000000
71 # define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
73 #ifndef CONFIG_8260_CLKIN
74 #define CONFIG_8260_CLKIN 66000000 /* in Hz */
77 #define CONFIG_BAUDRATE 115200
79 #define CONFIG_BOOTCOUNT_LIMIT
82 * Command line configuration.
84 #include <config_cmd_default.h>
86 #define CONFIG_CMD_DTT
87 #define CONFIG_CMD_ECHO
88 #define CONFIG_CMD_EEPROM
89 #define CONFIG_CMD_I2C
90 #define CONFIG_CMD_IMMAP
91 #define CONFIG_CMD_MII
92 #define CONFIG_CMD_PING
95 * Default environment settings
97 #define CONFIG_EXTRA_ENV_SETTINGS \
99 "u-boot_addr=100000\0" \
100 "kernel_addr=200000\0" \
101 "fdt_addr=400000\0" \
102 "rootpath=/opt/eldk-4.2/ppc_82xx\0" \
103 "u-boot=/tftpboot/mgcoge/u-boot.bin\0" \
104 "bootfile=/tftpboot/mgcoge/uImage\0" \
105 "fdt_file=/tftpboot/mgcoge/mgcoge.dtb\0" \
106 "load=tftp ${u-boot_addr} ${u-boot}\0" \
107 "update=prot off fe000000 fe03ffff; era fe000000 fe03ffff; " \
108 "cp.b ${u-boot_addr} fe000000 ${filesize};" \
109 "prot on fe000000 fe03ffff\0" \
110 "ramargs=setenv bootargs root=/dev/ram rw\0" \
111 "nfsargs=setenv bootargs root=/dev/nfs rw " \
112 "nfsroot=${serverip}:${rootpath}\0" \
113 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
114 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
115 "addip=setenv bootargs ${bootargs} " \
116 "ip=${ipaddr}:${serverip}:${gatewayip}:" \
117 "${netmask}:${hostname}:${netdev}:off panic=1\0" \
118 "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
119 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
120 "bootm ${kernel_addr} - ${fdt_addr}\0" \
121 "net_self=tftp ${kernel_addr} ${bootfile}; " \
122 "tftp ${fdt_addr} ${fdt_file}; " \
123 "tftp ${ramdisk_addr} ${ramdisk_file}; " \
124 "run ramargs addip; " \
125 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
127 #define CONFIG_BOOTCOMMAND "run net_nfs"
128 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
130 #undef CONFIG_WATCHDOG /* disable platform specific watchdog */
133 * Miscellaneous configurable options
135 #define CONFIG_SYS_HUSH_PARSER
136 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
137 #define CONFIG_SYS_LONGHELP /* undef to save memory */
138 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
139 #define CONFIG_HUSH_INIT_VAR 1
140 #if defined(CONFIG_CMD_KGDB)
141 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
143 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
145 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
146 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
147 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
149 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
150 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
152 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
154 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
156 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
158 #define CONFIG_SYS_SDRAM_BASE 0x00000000
159 #define CONFIG_SYS_FLASH_BASE 0xFE000000
160 #define CONFIG_SYS_FLASH_SIZE 32
161 #define CONFIG_SYS_FLASH_CFI
162 #define CONFIG_FLASH_CFI_DRIVER
163 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
164 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */
166 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
167 #define CONFIG_SYS_FLASH_SIZE_1 64
169 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
171 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
172 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
173 #define CONFIG_SYS_RAMBOOT
176 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
178 #define CONFIG_ENV_IS_IN_FLASH
180 #ifdef CONFIG_ENV_IS_IN_FLASH
181 #define CONFIG_ENV_SECT_SIZE 0x20000
182 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
183 #endif /* CONFIG_ENV_IS_IN_FLASH */
185 /* enable I2C and select the hardware/software driver */
186 #undef CONFIG_HARD_I2C /* I2C with hardware support */
187 #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
188 #define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */
189 #define CONFIG_SYS_I2C_SLAVE 0x7F
192 * Software (bit-bang) I2C driver configuration
195 #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
196 #define I2C_ACTIVE (iop->pdir |= 0x00010000)
197 #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
198 #define I2C_READ ((iop->pdat & 0x00010000) != 0)
199 #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
200 else iop->pdat &= ~0x00010000
201 #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
202 else iop->pdat &= ~0x00020000
203 #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
205 #define CONFIG_I2C_MULTI_BUS 1
206 #define CONFIG_I2C_CMD_TREE 1
207 #define CONFIG_SYS_MAX_I2C_BUS 2
208 #define CONFIG_SYS_I2C_INIT_BOARD 1
209 #define CONFIG_I2C_MUX 1
212 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
213 #define CONFIG_SYS_I2C_MULTI_EEPROMS 1
214 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
218 /* Support the IVM EEprom */
219 #define CONFIG_SYS_IVM_EEPROM_ADR 0x50
220 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN 0x400
221 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN 0x100
223 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
224 #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
225 #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
226 #define CONFIG_SYS_DTT_MAX_TEMP 70
227 #define CONFIG_SYS_DTT_LOW_TEMP -30
228 #define CONFIG_SYS_DTT_HYSTERESIS 3
229 #define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
231 #define CONFIG_SYS_IMMR 0xF0000000
233 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
234 #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
235 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
236 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
237 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
239 /* Hard reset configuration word */
240 #define CONFIG_SYS_HRCW_MASTER 0x0604b211
243 #define CONFIG_SYS_HRCW_SLAVE1 0
244 #define CONFIG_SYS_HRCW_SLAVE2 0
245 #define CONFIG_SYS_HRCW_SLAVE3 0
246 #define CONFIG_SYS_HRCW_SLAVE4 0
247 #define CONFIG_SYS_HRCW_SLAVE5 0
248 #define CONFIG_SYS_HRCW_SLAVE6 0
249 #define CONFIG_SYS_HRCW_SLAVE7 0
251 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
252 #define BOOTFLAG_WARM 0x02 /* Software reboot */
254 #define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
255 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
257 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
258 #if defined(CONFIG_CMD_KGDB)
259 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
262 #define CONFIG_SYS_HID0_INIT 0
263 #define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
265 #define CONFIG_SYS_HID2 0
267 #define CONFIG_SYS_SIUMCR 0x4020c200
268 #define CONFIG_SYS_SYPCR 0xFFFFFFC3
269 #define CONFIG_SYS_BCR 0x10000000
270 #define CONFIG_SYS_SCCR (SCCR_PCI_MODE | SCCR_PCI_MODCK)
272 /*-----------------------------------------------------------------------
273 * RMR - Reset Mode Register 5-5
274 *-----------------------------------------------------------------------
275 * turn on Checkstop Reset Enable
277 #define CONFIG_SYS_RMR 0
279 /*-----------------------------------------------------------------------
280 * TMCNTSC - Time Counter Status and Control 4-40
281 *-----------------------------------------------------------------------
282 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
283 * and enable Time Counter
285 #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
287 /*-----------------------------------------------------------------------
288 * PISCR - Periodic Interrupt Status and Control 4-42
289 *-----------------------------------------------------------------------
290 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
293 #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
295 /*-----------------------------------------------------------------------
296 * RCCR - RISC Controller Configuration 13-7
297 *-----------------------------------------------------------------------
299 #define CONFIG_SYS_RCCR 0
302 * Init Memory Controller:
304 * Bank Bus Machine PortSz Device
305 * ---- --- ------- ------ ------
306 * 0 60x GPCM 8 bit FLASH
307 * 1 60x SDRAM 32 bit SDRAM
308 * 3 60x GPCM 8 bit GPIO/PIGGY
309 * 5 60x GPCM 16 bit CFG-Flash
314 #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
319 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
326 /* Bank 1 - 60x bus SDRAM
328 #define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
329 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */
331 #define CONFIG_SYS_MPTPR 0x1800
333 /*-----------------------------------------------------------------------------
334 * Address for Mode Register Set (MRS) command
335 *-----------------------------------------------------------------------------
337 #define CONFIG_SYS_MRS_OFFS 0x00000110
338 #define CONFIG_SYS_PSRT 0x0e
340 #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
345 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1
347 /* SDRAM initialization values
350 #define CONFIG_SYS_OR1 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
352 ORxS_ROWST_PBI0_A7 |\
355 #define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\
356 PSDMR_BSMA_A14_A16 |\
357 PSDMR_SDA10_PBI0_A9 |\
365 /* GPIO/PIGGY on CS3 initialization values
367 #define CONFIG_SYS_PIGGY_BASE 0x30000000
368 #define CONFIG_SYS_PIGGY_SIZE 128
370 #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
371 BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
373 #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
374 ORxG_CSNT | ORxG_ACS_DIV2 |\
375 ORxG_SCY_3_CLK | ORxG_TRLX )
377 /* CFG-Flash on CS5 initialization values
379 #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
380 BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
382 #define CONFIG_SYS_OR5_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1) |\
383 ORxG_CSNT | ORxG_ACS_DIV2 |\
384 ORxG_SCY_5_CLK | ORxG_TRLX )
386 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */
388 /* pass open firmware flat tree */
389 #define CONFIG_OF_LIBFDT 1
390 #define CONFIG_OF_BOARD_SETUP 1
392 #define OF_CPU "PowerPC,8247@0"
393 #define OF_SOC "soc@f0000000"
394 #define OF_TBCLK (bd->bi_busfreq / 4)
395 #define OF_STDOUT_PATH "/soc/cpm/serial@11a90"
397 #endif /* __CONFIG_H */