include/configs/mgsuvd.h

   1 /*
   2  * (C) Copyright 2007
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC866           1       /* This is a MPC866 CPU         */
  37 #define CONFIG_MGSUVD           1       /* ...on a mgsuvd board */
  38
  39 /* Do boardspecific init */
  40 #define CONFIG_BOARD_EARLY_INIT_R       1
  41
  42 #define CONFIG_8xx_GCLK_FREQ            66000000
  43
  44 #define CONFIG_SYS_SMC_UCODE_PATCH      1       /* Relocate SMC1 */
  45 #define CONFIG_SYS_SMC_DPMEM_OFFSET     0x1fc0
  46 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  47
  48 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115kbps   */
  49
  50 #define CONFIG_BOOTCOUNT_LIMIT
  51 #define CONFIG_SYS_CPM_BOOTCOUNT_ADDR   0x1eb0  /* In case of SMC relocation, the
  52                                          * default value is not working */
  53
  54 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  55
  56 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  57
  58 #define CONFIG_PREBOOT  "echo;" \
  59         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  60         "echo"
  61
  62 #undef  CONFIG_BOOTARGS
  63
  64 #define CONFIG_EXTRA_ENV_SETTINGS                                               \
  65         "netdev=eth0\0"                                                         \
  66         "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0"     \
  67         "nfsargs=setenv bootargs root=/dev/nfs rw "                             \
  68                 "nfsroot=${serverip}:${rootpath}\0"                             \
  69         "ramargs=setenv bootargs root=/dev/ram rw\0"                            \
  70         "addip=setenv bootargs ${bootargs} "                                    \
  71                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"              \
  72                 ":${hostname}:${netdev}:off panic=1\0"                          \
  73         "flash_nfs=run nfsargs addip;"                                          \
  74                 "bootm ${kernel_addr}\0"                                        \
  75         "flash_self=run ramargs addip;"                                         \
  76                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                        \
  77         "net_nfs=tftp ${kernel_addr} ${bootfile}; "                             \
  78                 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;"      \
  79                 "bootm ${kernel_addr} - ${fdt_addr}\0"                          \
  80         "rootpath=/opt/eldk/ppc_8xx\0"                                          \
  81         "bootfile=/tftpboot/mgsuvd/uImage\0"                                    \
  82         "fdt_addr=400000\0"                                                     \
  83         "kernel_addr=200000\0"                                                  \
  84         "fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0"                                \
  85         "load=tftp 200000 ${u-boot}\0"                                          \
  86         "update=protect off f0000000 +${filesize};"                             \
  87                 "erase f0000000 +${filesize};"                                  \
  88                 "cp.b 200000 f0000000 ${filesize};"                             \
  89                 "protect on f0000000 +${filesize}\0"                            \
  90         ""
  91 #define CONFIG_BOOTCOMMAND      "run flash_self"
  92
  93 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  94 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  95
  96 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  97
  98 /*
  99  * BOOTP options
 100  */
 101 #define CONFIG_BOOTP_SUBNETMASK
 102 #define CONFIG_BOOTP_GATEWAY
 103 #define CONFIG_BOOTP_HOSTNAME
 104 #define CONFIG_BOOTP_BOOTPATH
 105 #define CONFIG_BOOTP_BOOTFILESIZE
 106
 107 #undef CONFIG_RTC_MPC8xx                /* MPC866 does not support RTC  */
 108
 109 #define CONFIG_TIMESTAMP                /* but print image timestmps    */
 110
 111 /*
 112  * Command line configuration.
 113  */
 114 #include <config_cmd_default.h>
 115
 116 #define CONFIG_CMD_ASKENV
 117 #define CONFIG_CMD_DHCP
 118 #define CONFIG_CMD_DTT
 119 #define CONFIG_CMD_EEPROM
 120 #define CONFIG_CMD_I2C
 121 #define CONFIG_CMD_NFS
 122 #define CONFIG_CMD_PING
 123
 124 /*
 125  * Miscellaneous configurable options
 126  */
 127 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 128 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 129
 130 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 131 #define CONFIG_SYS_HUSH_PARSER          1       /* Use the HUSH parser          */
 132 #ifdef  CONFIG_SYS_HUSH_PARSER
 133 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 134 #define CONFIG_HUSH_INIT_VAR    1
 135 #endif
 136
 137 #if defined(CONFIG_CMD_KGDB)
 138 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 139 #else
 140 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 141 #endif
 142 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 143 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 144 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 145
 146 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 147 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 148
 149 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 150
 151 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 152
 153 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 154
 155 /*
 156  * Low Level Configuration Settings
 157  * (address mappings, register initial values, etc.)
 158  * You should know what you are doing if you make changes here.
 159  */
 160 /*-----------------------------------------------------------------------
 161  * Internal Memory Mapped Register
 162  */
 163 #define CONFIG_SYS_IMMR         0xFFF00000
 164
 165 /*-----------------------------------------------------------------------
 166  * Definitions for initial stack pointer and data area (in DPRAM)
 167  */
 168 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 169 #define CONFIG_SYS_INIT_RAM_END 0x2F00  /* End of used area in DPRAM    */
 170 #define CONFIG_SYS_GBL_DATA_SIZE        64  /* size in bytes reserved for initial data */
 171 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 172 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 173
 174 /*-----------------------------------------------------------------------
 175  * Start addresses for the final memory configuration
 176  * (Set up by the startup code)
 177  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 178  */
 179 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 180 #define CONFIG_SYS_FLASH_BASE           0xf0000000
 181 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 182 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 183 #define CONFIG_SYS_MALLOC_LEN           (256 << 10)     /* Reserve 256 kB for malloc()  */
 184
 185 /*
 186  * For booting Linux, the board info and command line data
 187  * have to be in the first 8 MB of memory, since this is
 188  * the maximum mapped by the Linux kernel during initialization.
 189  */
 190 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 191
 192 /*-----------------------------------------------------------------------
 193  * FLASH organization
 194  */
 195 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 196 #define CONFIG_SYS_FLASH_SIZE           32
 197 #define CONFIG_SYS_FLASH_CFI
 198 #define CONFIG_FLASH_CFI_DRIVER
 199 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 200
 201
 202 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 203 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 204
 205 #define CONFIG_ENV_IS_IN_FLASH  1
 206 #define CONFIG_ENV_OFFSET               0x40000 /*   Offset   of Environment Sector     */
 207 #define CONFIG_ENV_SIZE         0x08000 /* Total Size of Environment Sector     */
 208 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Total Size of Environment Sector     */
 209
 210 /* Address and size of Redundant Environment Sector     */
 211 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 212 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 213
 214 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 215
 216 /*-----------------------------------------------------------------------
 217  * Cache Configuration
 218  */
 219 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 220 #if defined(CONFIG_CMD_KGDB)
 221 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 222 #endif
 223
 224 /*-----------------------------------------------------------------------
 225  * SYPCR - System Protection Control                            11-9
 226  * SYPCR can only be written once after reset!
 227  *-----------------------------------------------------------------------
 228  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 229  */
 230 #define CONFIG_SYS_SYPCR        0xffffff89
 231
 232 /*-----------------------------------------------------------------------
 233  * SIUMCR - SIU Module Configuration                            11-6
 234  *-----------------------------------------------------------------------
 235  */
 236 #define CONFIG_SYS_SIUMCR       0x00610480
 237
 238 /*-----------------------------------------------------------------------
 239  * TBSCR - Time Base Status and Control                         11-26
 240  *-----------------------------------------------------------------------
 241  * Clear Reference Interrupt Status, Timebase freezing enabled
 242  */
 243 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 244
 245 /*-----------------------------------------------------------------------
 246  * PISCR - Periodic Interrupt Status and Control                11-31
 247  *-----------------------------------------------------------------------
 248  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 249  */
 250 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 251
 252 /*-----------------------------------------------------------------------
 253  * SCCR - System Clock and reset Control Register               15-27
 254  *-----------------------------------------------------------------------
 255  * Set clock output, timebase and RTC source and divider,
 256  * power management and some other internal clocks
 257  */
 258 #define SCCR_MASK       0x01800000
 259 #define CONFIG_SYS_SCCR 0x01800000
 260
 261 #define CONFIG_SYS_DER 0
 262
 263 /*
 264  * Init Memory Controller:
 265  *
 266  * BR0/1 and OR0/1 (FLASH)
 267  */
 268
 269 #define FLASH_BASE0_PRELIM      0xf0000000      /* FLASH bank #0        */
 270
 271 /* used to re-map FLASH both when starting from SRAM or FLASH:
 272  * restrict access enough to keep SRAM working (if any)
 273  * but not too much to meddle with FLASH accesses
 274  */
 275 #define CONFIG_SYS_REMAP_OR_AM          0x80000000      /* OR addr mask */
 276 #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000      /* OR addr mask */
 277
 278 /*
 279  * FLASH timing: Default value of OR0 after reset
 280  */
 281 #define CONFIG_SYS_OR0_PRELIM   0xfe000954
 282 #define CONFIG_SYS_BR0_PRELIM   0xf0000401
 283
 284 /*
 285  * BR1 and OR1 (SDRAM)
 286  *
 287  */
 288 #define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank #0        */
 289 #define SDRAM_MAX_SIZE          (64 << 20)      /* max 64 MB per bank   */
 290
 291 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 292 #define CONFIG_SYS_OR_TIMING_SDRAM      0x00000A00
 293
 294 #define CONFIG_SYS_OR1_PRELIM   0xfc000800
 295 #define CONFIG_SYS_BR1_PRELIM   (0x000000C0 | 0x01)
 296
 297 #define CONFIG_SYS_MPTPR        0x0200
 298 /* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
 299    1 Write loop Cycle (not used), 1 Timer Loop Cycle */
 300 #define CONFIG_SYS_MBMR 0x10964111
 301 #define CONFIG_SYS_MAR          0x00000088
 302
 303 /*
 304  * 4096 Rows from SDRAM example configuration
 305  * 1000 factor s -> ms
 306  * 64   PTP (pre-divider from MPTPR) from SDRAM example configuration
 307  * 4    Number of refresh cycles per period
 308  * 64   Refresh cycle in ms per number of rows
 309  */
 310 #define CONFIG_SYS_PTA_PER_CLK  ((4096 * 64 * 1000) / (4 * 64))
 311
 312 /* GPIO/PIGGY on CS3 initialization values
 313 */
 314 #define CONFIG_SYS_PIGGY_BASE   (0x30000000)
 315 #define CONFIG_SYS_OR3_PRELIM   (0xfe000d24)
 316 #define CONFIG_SYS_BR3_PRELIM   (0x30000401)
 317
 318 /*
 319  * Internal Definitions
 320  *
 321  * Boot Flags
 322  */
 323 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 324 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 325
 326 #define CONFIG_SCC3_ENET
 327 #define CONFIG_ETHPRIME         "SCC ETHERNET"
 328 #define CONFIG_HAS_ETH0
 329
 330 /* pass open firmware flat tree */
 331 #define CONFIG_OF_LIBFDT        1
 332 #define CONFIG_OF_BOARD_SETUP   1
 333
 334 #define OF_CPU                  "PowerPC,866@0"
 335 #define OF_SOC                  "soc@fff00000"
 336 #define OF_TBCLK                (bd->bi_busfreq / 4)
 337 #define OF_STDOUT_PATH          "/soc/cpm/serial@a80"
 338
 339 /* enable I2C and select the hardware/software driver */
 340 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 341 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 342 #define CONFIG_SYS_I2C_SPEED            50000   /* I2C speed and slave address  */
 343 #define CONFIG_SYS_I2C_SLAVE            0x7F
 344 #define I2C_SOFT_DECLARATIONS
 345
 346 /*
 347  * Software (bit-bang) I2C driver configuration
 348  */
 349 #define I2C_BASE_DIR    (CONFIG_SYS_PIGGY_BASE + 0x04)
 350 #define I2C_BASE_PORT   (CONFIG_SYS_PIGGY_BASE + 0x09)
 351
 352 #define SDA_BIT         0x40
 353 #define SCL_BIT         0x80
 354 #define SDA_CONF        0x1000
 355 #define SCL_CONF        0x2000
 356
 357 #define I2C_ACTIVE      do {} while (0)
 358 #define I2C_TRISTATE    do {} while (0)
 359 #define I2C_READ        i2c_soft_read_pin ()
 360 #define I2C_SDA(bit)    if(bit) { \
 361                                 *(unsigned short *)(I2C_BASE_DIR) &=  ~SDA_CONF; \
 362                                 } \
 363                         else    { \
 364                                 *(unsigned char *)(I2C_BASE_PORT) &= ~SDA_BIT; \
 365                                 *(unsigned short *)(I2C_BASE_DIR) |= SDA_CONF; \
 366                                 }
 367 #define I2C_SCL(bit)    if(bit) { \
 368                                 *(unsigned short *)(I2C_BASE_DIR) &=  ~SCL_CONF; \
 369                                 } \
 370                         else    { \
 371                                 *(unsigned char *)(I2C_BASE_PORT) &= ~SCL_BIT; \
 372                                 *(unsigned short *)(I2C_BASE_DIR) |= SCL_CONF; \
 373                                 }
 374 #define I2C_DELAY       udelay(50)      /* 1/4 I2C clock duration */
 375
 376 #define CONFIG_I2C_MULTI_BUS    1
 377 #define CONFIG_I2C_CMD_TREE     1
 378 #define CONFIG_SYS_MAX_I2C_BUS          2
 379 #define CONFIG_SYS_I2C_INIT_BOARD       1
 380 #define CONFIG_I2C_MUX          1
 381
 382 /* EEprom support */
 383 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 384 #define CONFIG_SYS_I2C_MULTI_EEPROMS    1
 385 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
 386 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 387 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 388
 389 /* Support the IVM EEprom */
 390 #define CONFIG_SYS_IVM_EEPROM_ADR       0x50
 391 #define CONFIG_SYS_IVM_EEPROM_MAX_LEN   0x400
 392 #define CONFIG_SYS_IVM_EEPROM_PAGE_LEN  0x100
 393
 394 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 395 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 396 #define CONFIG_DTT_SENSORS      {0, 2, 4, 6}    /* Sensor addresses             */
 397 #define CONFIG_SYS_DTT_MAX_TEMP 70
 398 #define CONFIG_SYS_DTT_LOW_TEMP -30
 399 #define CONFIG_SYS_DTT_HYSTERESIS       3
 400 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 401
 402 #endif  /* __CONFIG_H */