include/configs/ml401.h

   1 /*
   2  * (C) Copyright 2007 Czech Technical University.
   3  *
   4  * Michal SIMEK <monstr@seznam.cz>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef __CONFIG_H
  26 #define __CONFIG_H
  27
  28 #include "../board/xilinx/ml401/xparameters.h"
  29
  30 #define CONFIG_MICROBLAZE       1       /* MicroBlaze CPU */
  31 #define MICROBLAZE_V5           1
  32 #define CONFIG_ML401            1       /* ML401 Board */
  33
  34 /* uart */
  35 #define CONFIG_SERIAL_BASE      XILINX_UART_BASEADDR
  36 #define CONFIG_BAUDRATE         XILINX_UART_BAUDRATE
  37 #define CFG_BAUDRATE_TABLE      { CONFIG_BAUDRATE }
  38
  39 /* setting reset address */
  40 /*#define       CFG_RESET_ADDRESS       TEXT_BASE*/
  41
  42 /* ethernet */
  43 #define CONFIG_EMACLITE         1
  44 #define XPAR_EMAC_0_DEVICE_ID   XPAR_OPB_ETHERNET_0_DEVICE_ID
  45
  46 /* gpio */
  47 #define CFG_GPIO_0              1
  48 #define CFG_GPIO_0_ADDR         XILINX_GPIO_BASEADDR
  49
  50 /* interrupt controller */
  51 #define CFG_INTC_0              1
  52 #define CFG_INTC_0_ADDR         XILINX_INTC_BASEADDR
  53 #define CFG_INTC_0_NUM          XILINX_INTC_NUM_INTR_INPUTS
  54
  55 /* timer */
  56 #define CFG_TIMER_0             1
  57 #define CFG_TIMER_0_ADDR        XILINX_TIMER_BASEADDR
  58 #define CFG_TIMER_0_IRQ         XILINX_TIMER_IRQ
  59 #define FREQUENCE               XILINX_CLOCK_FREQ
  60 #define CFG_TIMER_0_PRELOAD     ( FREQUENCE/1000 )
  61
  62 /* FSL */
  63 #define CFG_FSL_2
  64 #define FSL_INTR_2      1
  65
  66 /*
  67  * memory layout - Example
  68  * TEXT_BASE = 0x1200_0000;
  69  * CFG_SRAM_BASE = 0x1000_0000;
  70  * CFG_SRAM_SIZE = 0x0400_0000;
  71  *
  72  * CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
  73  * CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
  74  * CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
  75  *
  76  * 0x1000_0000  CFG_SDRAM_BASE
  77  *                                      FREE
  78  * 0x1200_0000  TEXT_BASE
  79  *              U-BOOT code
  80  * 0x1202_0000
  81  *                                      FREE
  82  *
  83  *                                      STACK
  84  * 0x13F7_F000  CFG_MALLOC_BASE
  85  *                                      MALLOC_AREA     256kB   Alloc
  86  * 0x11FB_F000  CFG_MONITOR_BASE
  87  *                                      MONITOR_CODE    256kB   Env
  88  * 0x13FF_F000  CFG_GBL_DATA_OFFSET
  89  *                                      GLOBAL_DATA     4kB     bd, gd
  90  * 0x1400_0000  CFG_SDRAM_BASE + CFG_SDRAM_SIZE
  91  */
  92
  93 /* ddr sdram - main memory */
  94 #define CFG_SDRAM_BASE          XILINX_RAM_START
  95 #define CFG_SDRAM_SIZE          XILINX_RAM_SIZE
  96 #define CFG_MEMTEST_START       CFG_SDRAM_BASE
  97 #define CFG_MEMTEST_END         (CFG_SDRAM_BASE + 0x1000)
  98
  99 /* global pointer */
 100 #define CFG_GBL_DATA_SIZE       0x1000  /* size of global data */
 101 /* start of global data */
 102 #define CFG_GBL_DATA_OFFSET     (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE)
 103
 104 /* monitor code */
 105 #define SIZE                    0x40000
 106 #define CFG_MONITOR_LEN         SIZE
 107 #define CFG_MONITOR_BASE        (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
 108 #define CFG_MONITOR_END         (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 109 #define CFG_MALLOC_LEN          SIZE
 110 #define CFG_MALLOC_BASE         (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
 111
 112 /* stack */
 113 #define CFG_INIT_SP_OFFSET      CFG_MONITOR_BASE
 114
 115 /*#define       RAMENV */
 116 #define FLASH
 117
 118 #ifdef FLASH
 119         #define CFG_FLASH_BASE          XILINX_FLASH_START
 120         #define CFG_FLASH_SIZE          XILINX_FLASH_SIZE
 121         #define CFG_FLASH_CFI           1
 122         #define CFG_FLASH_CFI_DRIVER    1
 123         #define CFG_FLASH_EMPTY_INFO    1       /* ?empty sector */
 124         #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks */
 125         #define CFG_MAX_FLASH_SECT      128     /* max number of sectors on one chip */
 126         #define CFG_FLASH_PROTECTION            /* hardware flash protection */
 127
 128         #ifdef  RAMENV
 129                 #define CFG_ENV_IS_NOWHERE      1
 130                 #define CFG_ENV_SIZE            0x1000
 131                 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - CFG_ENV_SIZE)
 132
 133         #else   /* !RAMENV */
 134                 #define CFG_ENV_IS_IN_FLASH     1
 135                 #define CFG_ENV_ADDR            0x40000
 136                 #define CFG_ENV_SECT_SIZE       0x40000 /* 256K(one sector) for env */
 137                 #define CFG_ENV_SIZE            0x2000
 138         #endif /* !RAMBOOT */
 139 #else /* !FLASH */
 140         /* ENV in RAM */
 141         #define CFG_NO_FLASH            1
 142         #define CFG_ENV_IS_NOWHERE      1
 143         #define CFG_ENV_SIZE            0x1000
 144         #define CFG_ENV_ADDR            (CFG_MONITOR_BASE - CFG_ENV_SIZE)
 145         #define CFG_FLASH_PROTECTION            /* hardware flash protection */
 146 #endif /* !FLASH */
 147
 148 /*
 149  * BOOTP options
 150  */
 151 #define CONFIG_BOOTP_BOOTFILESIZE
 152 #define CONFIG_BOOTP_BOOTPATH
 153 #define CONFIG_BOOTP_GATEWAY
 154 #define CONFIG_BOOTP_HOSTNAME
 155
 156
 157 /*
 158  * Command line configuration.
 159  */
 160 #include <config_cmd_default.h>
 161
 162 #define CONFIG_CMD_ASKENV
 163 #define CONFIG_CMD_AUTOSCRIPT
 164 #define CONFIG_CMD_BDI
 165 #define CONFIG_CMD_CACHE
 166 #define CONFIG_CMD_EXT2
 167 #define CONFIG_CMD_FAT
 168 #define CONFIG_CMD_IMI
 169 #define CONFIG_CMD_IRQ
 170 #define CONFIG_CMD_LOADB
 171 #define CONFIG_CMD_LOADS
 172 #define CONFIG_CMD_MEMORY
 173 #define CONFIG_CMD_MISC
 174 #define CONFIG_CMD_MFSL
 175 #define CONFIG_CMD_NET
 176 #define CONFIG_CMD_PING
 177 #define CONFIG_CMD_RUN
 178
 179 #if defined(FLASH)
 180         #define CONFIG_CMD_ECHO
 181         #define CONFIG_CMD_FLASH
 182         #define CONFIG_CMD_IMLS
 183         #define CONFIG_CMD_JFFS2
 184
 185         #if !defined(RAMENV)
 186                 #define CONFIG_CMD_ENV
 187                 #define CONFIG_CMD_SAVES
 188         #endif
 189 #endif
 190
 191 #if defined(CONFIG_CMD_JFFS2)
 192 /* JFFS2 partitions */
 193 #define CONFIG_JFFS2_CMDLINE    /* mtdparts command line support */
 194 #define MTDIDS_DEFAULT          "nor0=ml401-0"
 195
 196 /* default mtd partition table */
 197 #define MTDPARTS_DEFAULT        "mtdparts=ml401-0:256k(u-boot),"\
 198                                 "256k(env),3m(kernel),1m(romfs),"\
 199                                 "1m(cramfs),-(jffs2)"
 200 #endif
 201
 202 /* Miscellaneous configurable options */
 203 #define CFG_PROMPT      "U-Boot-mONStR> "
 204 #define CFG_CBSIZE      512     /* size of console buffer */
 205 #define CFG_PBSIZE      (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
 206 #define CFG_MAXARGS     15      /* max number of command args */
 207 #define CFG_LONGHELP
 208 #define CFG_LOAD_ADDR   0x12000000 /* default load address */
 209
 210 #define CONFIG_BOOTDELAY        30
 211 #define CONFIG_BOOTARGS         "root=romfs"
 212 #define CONFIG_HOSTNAME         "ml401"
 213 #define CONFIG_BOOTCOMMAND      "base 0;tftp 11000000 image.img;bootm"
 214 #define CONFIG_IPADDR           192.168.0.3
 215 #define CONFIG_SERVERIP         192.168.0.5
 216 #define CONFIG_GATEWAYIP        192.168.0.1
 217 #define CONFIG_ETHADDR          00:E0:0C:00:00:FD
 218
 219 /* architecture dependent code */
 220 #define CFG_USR_EXCEP   /* user exception */
 221 #define CFG_HZ  1000
 222
 223 /* system ace */
 224 #define CONFIG_SYSTEMACE
 225 /* #define DEBUG_SYSTEMACE */
 226 #define SYSTEMACE_CONFIG_FPGA
 227 #define CFG_SYSTEMACE_BASE      XILINX_SYSACE_BASEADDR
 228 #define CFG_SYSTEMACE_WIDTH     XILINX_SYSACE_MEM_WIDTH
 229 #define CONFIG_DOS_PARTITION
 230
 231 #define CONFIG_PREBOOT          "echo U-BOOT for ML401;setenv preboot;echo"
 232
 233 #define CONFIG_EXTRA_ENV_SETTINGS       "unlock=yes\0" /* hardware flash protection */\
 234                                         "nor0=ml401-0\0"\
 235                                         "mtdparts=mtdparts=ml401-0:"\
 236                                         "256k(u-boot),256k(env),3m(kernel),"\
 237                                         "1m(romfs),1m(cramfs),-(jffs2)\0"
 238
 239 #endif  /* __CONFIG_H */