include/configs/mpc5121ads.h

   1 /*
   2  * (C) Copyright 2007-2009 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * MPC5121ADS board configuration file
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_MPC5121ADS 1
  31 /*
  32  * Memory map for the MPC5121ADS board:
  33  *
  34  * 0x0000_0000 - 0x0FFF_FFFF    DDR RAM (256 MB)
  35  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
  36  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  37  * 0x8200_0000 - 0x8200_001F    CPLD (32 B)
  38  * 0x8400_0000 - 0x82FF_FFFF    PCI I/O space (16 MB)
  39  * 0xA000_0000 - 0xAFFF_FFFF    PCI memory space (256 MB)
  40  * 0xB000_0000 - 0xBFFF_FFFF    PCI memory mapped I/O space (256 MB)
  41  * 0xFC00_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
  42  */
  43
  44 /*
  45  * High Level Configuration Options
  46  */
  47 #define CONFIG_E300             1       /* E300 Family */
  48 #define CONFIG_MPC512X          1       /* MPC512X family */
  49 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  50 #undef CONFIG_FSL_DIU_LOGO_BMP          /* Don't include FSL DIU binary bmp */
  51
  52 /* video */
  53 #undef CONFIG_VIDEO
  54
  55 #if defined(CONFIG_VIDEO)
  56 #define CONFIG_CFB_CONSOLE
  57 #define CONFIG_VGA_AS_SINGLE_DEVICE
  58 #endif
  59
  60 /* CONFIG_PCI is defined at config time */
  61
  62 #ifdef CONFIG_MPC5121ADS_REV2
  63 #define CONFIG_SYS_MPC512X_CLKIN        66000000        /* in Hz */
  64 #else
  65 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  66 #define CONFIG_PCI
  67 #endif
  68
  69 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
  70 #define CONFIG_MISC_INIT_R
  71
  72 #define CONFIG_SYS_IMMR         0x80000000
  73 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR+0x2100)
  74
  75 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  76 #define CONFIG_SYS_MEMTEST_END          0x00400000
  77
  78 /*
  79  * DDR Setup - manually set all parameters as there's no SPD etc.
  80  */
  81 #ifdef CONFIG_MPC5121ADS_REV2
  82 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  83 #else
  84 #define CONFIG_SYS_DDR_SIZE             512             /* MB */
  85 #endif
  86 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  87 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  88
  89 /* DDR Controller Configuration
  90  *
  91  * SYS_CFG:
  92  *      [31:31] MDDRC Soft Reset:       Diabled
  93  *      [30:30] DRAM CKE pin:           Enabled
  94  *      [29:29] DRAM CLK:               Enabled
  95  *      [28:28] Command Mode:           Enabled (For initialization only)
  96  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
  97  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
  98  *      [20:19] Read Test:              DON'T USE
  99  *      [18:18] Self Refresh:           Enabled
 100  *      [17:17] 16bit Mode:             Disabled
 101  *      [16:13] Ready Delay:            2
 102  *      [12:12] Half DQS Delay:         Disabled
 103  *      [11:11] Quarter DQS Delay:      Disabled
 104  *      [10:08] Write Delay:            2
 105  *      [07:07] Early ODT:              Disabled
 106  *      [06:06] On DIE Termination:     Disabled
 107  *      [05:05] FIFO Overflow Clear:    DON'T USE here
 108  *      [04:04] FIFO Underflow Clear:   DON'T USE here
 109  *      [03:03] FIFO Overflow Pending:  DON'T USE here
 110  *      [02:02] FIFO Underlfow Pending: DON'T USE here
 111  *      [01:01] FIFO Overlfow Enabled:  Enabled
 112  *      [00:00] FIFO Underflow Enabled: Enabled
 113  * TIME_CFG0
 114  *      [31:16] DRAM Refresh Time:      0 CSB clocks
 115  *      [15:8]  DRAM Command Time:      0 CSB clocks
 116  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 117  * TIME_CFG1
 118  *      [31:26] DRAM tRFC:
 119  *      [25:21] DRAM tWR1:
 120  *      [20:17] DRAM tWRT1:
 121  *      [16:11] DRAM tDRR:
 122  *      [10:05] DRAM tRC:
 123  *      [04:00] DRAM tRAS:
 124  * TIME_CFG2
 125  *      [31:28] DRAM tRCD:
 126  *      [27:23] DRAM tFAW:
 127  *      [22:19] DRAM tRTW1:
 128  *      [18:15] DRAM tCCD:
 129  *      [14:10] DRAM tRTP:
 130  *      [09:05] DRAM tRP:
 131  *      [04:00] DRAM tRPA
 132  */
 133 #ifdef CONFIG_MPC5121ADS_REV2
 134 #define CONFIG_SYS_MDDRC_SYS_CFG        0xF8604A00
 135 #define CONFIG_SYS_MDDRC_SYS_CFG_RUN    0xE8604A00
 136 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x54EC1168
 137 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x35210864
 138 #else
 139 #define CONFIG_SYS_MDDRC_SYS_CFG         0xFA804A00
 140 #define CONFIG_SYS_MDDRC_SYS_CFG_RUN     0xEA804A00
 141 #define CONFIG_SYS_MDDRC_TIME_CFG1       0x68EC1168
 142 #define CONFIG_SYS_MDDRC_TIME_CFG2       0x34310864
 143 #endif
 144 #define CONFIG_SYS_MDDRC_SYS_CFG_EN     0xF0000000
 145 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x00003D2E
 146 #define CONFIG_SYS_MDDRC_TIME_CFG0_RUN  0x06183D2E
 147
 148 #define CONFIG_SYS_MICRON_NOP           0x01380000
 149 #define CONFIG_SYS_MICRON_PCHG_ALL      0x01100400
 150 #define CONFIG_SYS_MICRON_EM2           0x01020000
 151 #define CONFIG_SYS_MICRON_EM3           0x01030000
 152 #define CONFIG_SYS_MICRON_EN_DLL        0x01010000
 153 #define CONFIG_SYS_MICRON_RFSH          0x01080000
 154 #define CONFIG_SYS_MICRON_INIT_DEV_OP   0x01000432
 155 #define CONFIG_SYS_MICRON_OCD_DEFAULT   0x01010780
 156
 157 /* DDR Priority Manager Configuration */
 158 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 159 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 160 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 161 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 162 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 163 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 164 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 165 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 166 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 167 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 168 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 169 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 170 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 171 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 172 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 173 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 174 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 175 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 176 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 177 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 178 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 179 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 180 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 181
 182 /*
 183  * NOR FLASH on the Local Bus
 184  */
 185 #undef CONFIG_BKUP_FLASH
 186 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 187 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 188 #ifdef CONFIG_BKUP_FLASH
 189 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 190 #define CONFIG_SYS_FLASH_SIZE           0x00800000      /* max flash size in bytes */
 191 #else
 192 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of FLASH   */
 193 #define CONFIG_SYS_FLASH_SIZE           0x04000000      /* max flash size in bytes */
 194 #endif
 195 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 196 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 197 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 198 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max sectors per device */
 199
 200 #undef CONFIG_SYS_FLASH_CHECKSUM
 201
 202 /*
 203  * NAND FLASH
 204  * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon only)
 205  */
 206 #define CONFIG_CMD_NAND
 207 #define CONFIG_NAND_MPC5121_NFC
 208 #define CONFIG_SYS_NAND_BASE            0x40000000
 209
 210 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 211 #define NAND_MAX_CHIPS                  CONFIG_SYS_MAX_NAND_DEVICE
 212 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
 213
 214 /*
 215  * Configuration parameters for MPC5121 NAND driver
 216  */
 217 #define CONFIG_FSL_NFC_WIDTH 1
 218 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
 219 #define CONFIG_FSL_NFC_SPARE_SIZE 64
 220 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
 221
 222 /*
 223  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
 224  * window is 64KB
 225  */
 226 #define CONFIG_SYS_CPLD_BASE            0x82000000
 227 #define CONFIG_SYS_CPLD_SIZE            0x00010000      /* 64 KB */
 228
 229 #define CONFIG_SYS_SRAM_BASE            0x30000000
 230 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 231
 232 #define CONFIG_SYS_CS0_CFG              0x05059310      /* ALE active low, data size 4bytes */
 233 #define CONFIG_SYS_CS2_CFG              0x05059010      /* ALE active low, data size 1byte */
 234 #define CONFIG_SYS_CS_ALETIMING 0x00000005      /* Use alternative CS timing for CS0 and CS2 */
 235
 236 /* Use SRAM for initial stack */
 237 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE            /* Initial RAM address */
 238 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE            /* End of used area in RAM */
 239
 240 #define CONFIG_SYS_GBL_DATA_SIZE        0x100                   /* num bytes initial data */
 241 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 242 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 243
 244 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE               /* Start of monitor */
 245 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)            /* Reserve 512 kB for Mon */
 246 #ifdef  CONFIG_FSL_DIU_FB
 247 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 248 #else
 249 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 250 #endif
 251
 252 /*
 253  * Serial Port
 254  */
 255 #define CONFIG_CONS_INDEX     1
 256 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 257
 258 /*
 259  * Serial console configuration
 260  */
 261 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
 262 #if CONFIG_PSC_CONSOLE != 3
 263 #error CONFIG_PSC_CONSOLE must be 3
 264 #endif
 265 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
 266 #define CONFIG_SYS_BAUDRATE_TABLE  \
 267         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 268
 269 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
 270 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
 271 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
 272 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
 273
 274 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 275 /* Use the HUSH parser */
 276 #define CONFIG_SYS_HUSH_PARSER
 277 #ifdef  CONFIG_SYS_HUSH_PARSER
 278 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 279 #endif
 280
 281 /*
 282  * PCI
 283  */
 284 #ifdef CONFIG_PCI
 285
 286 /*
 287  * General PCI
 288  */
 289 #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
 290 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
 291 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000      /* 256M */
 292 #define CONFIG_SYS_PCI_MMIO_BASE        (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
 293 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 294 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000      /* 256M */
 295 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 296 #define CONFIG_SYS_PCI_IO_PHYS          0x84000000
 297 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000      /* 16M */
 298
 299
 300 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 301
 302 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 303
 304 #endif
 305
 306 /* I2C */
 307 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 308 #undef CONFIG_SOFT_I2C                  /* so disable bit-banged I2C */
 309 #define CONFIG_I2C_MULTI_BUS
 310 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 311 #define CONFIG_SYS_I2C_SLAVE            0x7F
 312 #if 0
 313 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 314 #endif
 315
 316 /*
 317  * IIM - IC Identification Module
 318  */
 319 #undef CONFIG_IIM
 320
 321 /*
 322  * EEPROM configuration
 323  */
 324 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM address */
 325 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* Atmel: AT24C32A-10TQ-2.7 */
 326 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
 327 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32-Byte Page Write Mode */
 328
 329 /*
 330  * Ethernet configuration
 331  */
 332 #define CONFIG_MPC512x_FEC      1
 333 #define CONFIG_NET_MULTI
 334 #define CONFIG_PHY_ADDR         0x1
 335 #define CONFIG_MII              1       /* MII PHY management           */
 336 #define CONFIG_FEC_AN_TIMEOUT   1
 337 #define CONFIG_HAS_ETH0
 338
 339 /*
 340  * Configure on-board RTC
 341  */
 342 #define CONFIG_RTC_M41T62                       /* use M41T62 rtc via i2 */
 343 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68              */
 344
 345 /*
 346  * Environment
 347  */
 348 #define CONFIG_ENV_IS_IN_FLASH  1
 349 /* This has to be a multiple of the Flash sector size */
 350 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 351 #define CONFIG_ENV_SIZE         0x2000
 352 #ifdef CONFIG_BKUP_FLASH
 353 #define CONFIG_ENV_SECT_SIZE    0x20000 /* one sector (256K) for env */
 354 #else
 355 #define CONFIG_ENV_SECT_SIZE    0x40000 /* one sector (256K) for env */
 356 #endif
 357
 358 /* Address and size of Redundant Environment Sector     */
 359 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 360 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 361
 362 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 363 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 364
 365 #include <config_cmd_default.h>
 366
 367 #define CONFIG_CMD_ASKENV
 368 #define CONFIG_CMD_DHCP
 369 #define CONFIG_CMD_I2C
 370 #define CONFIG_CMD_MII
 371 #define CONFIG_CMD_NFS
 372 #define CONFIG_CMD_PING
 373 #define CONFIG_CMD_REGINFO
 374 #define CONFIG_CMD_EEPROM
 375 #define CONFIG_CMD_DATE
 376 #undef CONFIG_CMD_FUSE
 377 #define CONFIG_CMD_IDE
 378 #define CONFIG_CMD_EXT2
 379
 380 #if defined(CONFIG_PCI)
 381 #define CONFIG_CMD_PCI
 382 #endif
 383
 384 #if defined(CONFIG_CMD_IDE)
 385 #define CONFIG_DOS_PARTITION
 386 #define CONFIG_MAC_PARTITION
 387 #define CONFIG_ISO_PARTITION
 388 #endif /* defined(CONFIG_CMD_IDE) */
 389
 390 /*
 391  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
 392  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
 393  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 394  * to chapter 36 of the MPC5121e Reference Manual.
 395  */
 396 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 397 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
 398
 399  /*
 400  * Miscellaneous configurable options
 401  */
 402 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 403 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 404 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 405
 406 #ifdef CONFIG_CMD_KGDB
 407         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 408 #else
 409         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 410 #endif
 411
 412
 413 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 414 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 415 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 416 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 417
 418 /*
 419  * For booting Linux, the board info and command line data
 420  * have to be in the first 8 MB of memory, since this is
 421  * the maximum mapped by the Linux kernel during initialization.
 422  */
 423 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 424
 425 /* Cache Configuration */
 426 #define CONFIG_SYS_DCACHE_SIZE          32768
 427 #define CONFIG_SYS_CACHELINE_SIZE       32
 428 #ifdef CONFIG_CMD_KGDB
 429 #define CONFIG_SYS_CACHELINE_SHIFT      5       /*log base 2 of the above value*/
 430 #endif
 431
 432 #define CONFIG_SYS_HID0_INIT    0x000000000
 433 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
 434 #define CONFIG_SYS_HID2 HID2_HBE
 435
 436 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 437
 438 /*
 439  * Internal Definitions
 440  *
 441  * Boot Flags
 442  */
 443 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 444 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 445
 446 #ifdef CONFIG_CMD_KGDB
 447 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 448 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 449 #endif
 450
 451 /*
 452  * Environment Configuration
 453  */
 454 #define CONFIG_TIMESTAMP
 455
 456 #define CONFIG_HOSTNAME         mpc5121ads
 457 #define CONFIG_BOOTFILE         mpc5121ads/uImage
 458 #define CONFIG_ROOTPATH         /opt/eldk/ppc_6xx
 459
 460 #define CONFIG_LOADADDR         400000  /* default location for tftp and bootm */
 461
 462 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 463 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 464
 465 #define CONFIG_BAUDRATE         115200
 466
 467 #define CONFIG_PREBOOT  "echo;" \
 468         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 469         "echo"
 470
 471 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 472         "u-boot_addr_r=200000\0"                                        \
 473         "kernel_addr_r=600000\0"                                        \
 474         "fdt_addr_r=880000\0"                                           \
 475         "ramdisk_addr_r=900000\0"                                       \
 476         "u-boot_addr=FFF00000\0"                                        \
 477         "kernel_addr=FFC40000\0"                                        \
 478         "fdt_addr=FFEC0000\0"                                           \
 479         "ramdisk_addr=FC040000\0"                                       \
 480         "ramdiskfile=mpc5121ads/uRamdisk\0"                             \
 481         "u-boot=mpc5121ads/u-boot.bin\0"                                \
 482         "bootfile=mpc5121ads/uImage\0"                                  \
 483         "fdtfile=mpc5121ads/mpc5121ads.dtb\0"                           \
 484         "rootpath=/opt/eldk/ppc_6xx\n"                                  \
 485         "netdev=eth0\0"                                                 \
 486         "consdev=ttyPSC0\0"                                             \
 487         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 488                 "nfsroot=${serverip}:${rootpath}\0"                     \
 489         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 490         "addip=setenv bootargs ${bootargs} "                            \
 491                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 492                 ":${hostname}:${netdev}:off panic=1\0"                  \
 493         "addtty=setenv bootargs ${bootargs} "                           \
 494                 "console=${consdev},${baudrate}\0"                      \
 495         "flash_nfs=run nfsargs addip addtty;"                           \
 496                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 497         "flash_self=run ramargs addip addtty;"                          \
 498                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 499         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 500                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 501                 "run nfsargs addip addtty;"                             \
 502                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 503         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 504                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 505                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 506                 "run ramargs addip addtty;"                             \
 507                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 508         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 509         "update=protect off ${u-boot_addr} +${filesize};"               \
 510                 "era ${u-boot_addr} +${filesize};"                      \
 511                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 512         "upd=run load update\0"                                         \
 513         ""
 514
 515 #define CONFIG_BOOTCOMMAND      "run flash_self"
 516
 517 #define CONFIG_OF_LIBFDT        1
 518 #define CONFIG_OF_BOARD_SETUP   1
 519 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 520
 521 #define OF_CPU                  "PowerPC,5121@0"
 522 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 523 #define OF_TBCLK                (bd->bi_busfreq / 4)
 524 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 525
 526 /*-----------------------------------------------------------------------
 527  * IDE/ATA stuff
 528  *-----------------------------------------------------------------------
 529  */
 530
 531 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 532 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 533 #undef  CONFIG_IDE_LED                  /* LED   for IDE not supported  */
 534
 535 #define CONFIG_IDE_RESET                /* reset for IDE supported      */
 536 #define CONFIG_IDE_PREINIT
 537
 538 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 539 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 540
 541 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 542 #define CONFIG_SYS_ATA_BASE_ADDR        get_pata_base()
 543
 544 /* Offset for data I/O                  RefMan MPC5121EE Table 28-10    */
 545 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x00A0)
 546
 547 /* Offset for normal register accesses  */
 548 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 549
 550 /* Offset for alternate registers       RefMan MPC5121EE Table 28-23    */
 551 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x00D8)
 552
 553 /* Interval between registers   */
 554 #define CONFIG_SYS_ATA_STRIDE           4
 555
 556 #define ATA_BASE_ADDR                   get_pata_base()
 557
 558 /*
 559  * Control register bit definitions
 560  */
 561 #define FSL_ATA_CTRL_FIFO_RST_B         0x80000000
 562 #define FSL_ATA_CTRL_ATA_RST_B          0x40000000
 563 #define FSL_ATA_CTRL_FIFO_TX_EN         0x20000000
 564 #define FSL_ATA_CTRL_FIFO_RCV_EN        0x10000000
 565 #define FSL_ATA_CTRL_DMA_PENDING        0x08000000
 566 #define FSL_ATA_CTRL_DMA_ULTRA          0x04000000
 567 #define FSL_ATA_CTRL_DMA_WRITE          0x02000000
 568 #define FSL_ATA_CTRL_IORDY_EN           0x01000000
 569
 570 #endif  /* __CONFIG_H */