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rename CFG_ macros to CONFIG_SYS
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1 /*
2 * Copyright (c) 2005 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2006
5 * Alex Bounine , Tundra Semiconductor Corp.
6 * Roy Zang , <tie-fei.zang@freescale.com> Freescale Corp.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 /*
28 * board specific configuration options for Freescale
29 * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
30 *
31 */
32
33 #ifndef __CONFIG_H
34 #define __CONFIG_H
35
36 /* Board Configuration Definitions */
37 /* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
38
39 #define CONFIG_MPC7448HPC2
40
41 #define CONFIG_74xx
42 #define CONFIG_HIGH_BATS /* High BATs supported */
43 #define CONFIG_ALTIVEC /* undef to disable */
44
45 #define CONFIG_SYS_BOARD_NAME "MPC7448 HPC II"
46 #define CONFIG_IDENT_STRING " Freescale MPC7448 HPC II"
47
48 #define CONFIG_SYS_OCN_CLK 133000000 /* 133 MHz */
49 #define CONFIG_SYS_CONFIG_BUS_CLK 133000000
50
51 #define CONFIG_SYS_CLK_SPREAD /* Enable Spread-Spectrum Clock generation */
52
53 #undef CONFIG_ECC /* disable ECC support */
54
55 /* Board-specific Initialization Functions to be called */
56 #define CONFIG_SYS_BOARD_ASM_INIT
57 #define CONFIG_BOARD_EARLY_INIT_F
58 #define CONFIG_BOARD_EARLY_INIT_R
59 #define CONFIG_MISC_INIT_R
60
61 #define CONFIG_HAS_ETH0
62 #define CONFIG_HAS_ETH1
63
64 #define CONFIG_ENV_OVERWRITE
65
66 /*
67 * High Level Configuration Options
68 * (easy to change)
69 */
70
71 #define CONFIG_BAUDRATE 115200 /* console baudrate = 115000 */
72
73 /*#define CONFIG_SYS_HUSH_PARSER */
74 #undef CONFIG_SYS_HUSH_PARSER
75
76 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
77
78 /* Pass open firmware flat tree */
79 #define CONFIG_OF_LIBFDT 1
80 #define CONFIG_OF_BOARD_SETUP 1
81
82 #define OF_CPU "PowerPC,7448@0"
83 #define OF_TSI "tsi108@c0000000"
84 #define OF_TBCLK (bd->bi_busfreq / 8)
85 #define OF_STDOUT_PATH "/tsi108@c0000000/serial@7808"
86
87 /*
88 * The following defines let you select what serial you want to use
89 * for your console driver.
90 *
91 * what to do:
92 * If you have hacked a serial cable onto the second DUART channel,
93 * change the CONFIG_SYS_DUART port from 1 to 0 below.
94 *
95 */
96
97 #define CONFIG_CONS_INDEX 1
98 #define CONFIG_SYS_NS16550
99 #define CONFIG_SYS_NS16550_SERIAL
100 #define CONFIG_SYS_NS16550_REG_SIZE 1
101 #define CONFIG_SYS_NS16550_CLK CONFIG_SYS_OCN_CLK * 8
102
103 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7808)
104 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_TSI108_CSR_RST_BASE+0x7C08)
105 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
106
107 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
108 #define CONFIG_ZERO_BOOTDELAY_CHECK
109
110 #undef CONFIG_BOOTARGS
111 /* #define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
112
113 #if (CONFIG_BOOTDELAY >= 0)
114 #define CONFIG_BOOTCOMMAND "tftpboot 0x400000 zImage.initrd.elf;\
115 setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
116 ip=$(ipaddr):$(serverip)$(bootargs_end); bootm 0x400000; "
117
118 #define CONFIG_BOOTARGS "console=ttyS0,115200"
119 #endif
120
121 #undef CONFIG_EXTRA_ENV_SETTINGS
122
123 #define CONFIG_SERIAL "No. 1"
124
125 /* Networking Configuration */
126
127 #define KSEG1ADDR(a) (a) /* Needed by the rtl8139 driver */
128
129 #define CONFIG_TSI108_ETH
130 #define CONFIG_TSI108_ETH_NUM_PORTS 2
131
132 #define CONFIG_NET_MULTI
133
134 #define CONFIG_BOOTFILE zImage.initrd.elf
135 #define CONFIG_LOADADDR 0x400000
136
137 /*-------------------------------------------------------------------------- */
138
139 #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
140 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
141
142 #undef CONFIG_WATCHDOG /* watchdog disabled */
143
144 /*
145 * BOOTP options
146 */
147 #define CONFIG_BOOTP_SUBNETMASK
148 #define CONFIG_BOOTP_GATEWAY
149 #define CONFIG_BOOTP_HOSTNAME
150 #define CONFIG_BOOTP_BOOTPATH
151 #define CONFIG_BOOTP_BOOTFILESIZE
152
153
154 /*
155 * Command line configuration.
156 */
157 #include <config_cmd_default.h>
158
159 #define CONFIG_CMD_ASKENV
160 #define CONFIG_CMD_CACHE
161 #define CONFIG_CMD_PCI
162 #define CONFIG_CMD_I2C
163 #define CONFIG_CMD_SDRAM
164 #define CONFIG_CMD_EEPROM
165 #define CONFIG_CMD_FLASH
166 #define CONFIG_CMD_ENV
167 #define CONFIG_CMD_BSP
168 #define CONFIG_CMD_DHCP
169 #define CONFIG_CMD_PING
170 #define CONFIG_CMD_DATE
171
172
173 /*set date in u-boot*/
174 #define CONFIG_RTC_M48T35A
175 #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000
176 #define CONFIG_SYS_NVRAM_SIZE 0x8000
177 /*
178 * Miscellaneous configurable options
179 */
180 #define CONFIG_VERSION_VARIABLE 1
181 #define CONFIG_TSI108_I2C
182
183 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C EEPROM page 1 */
184 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
185
186 #define CONFIG_SYS_LONGHELP /* undef to save memory */
187 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
188
189 #if defined(CONFIG_CMD_KGDB)
190 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
191 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
192 #else
193 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
194 #endif
195
196 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)/* Print Buffer Size */
197 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
198 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
199
200 #define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
201 #define CONFIG_SYS_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
202
203 #define CONFIG_SYS_LOAD_ADDR 0x00400000 /* default load address */
204
205 #define CONFIG_SYS_HZ 1000 /* decr freq: 1ms ticks */
206
207 /*
208 * Low Level Configuration Settings
209 * (address mappings, register initial values, etc.)
210 * You should know what you are doing if you make changes here.
211 */
212
213 /*-----------------------------------------------------------------------
214 * Definitions for initial stack pointer and data area
215 */
216
217 /*
218 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
219 * To an unused memory region. The stack will remain in cache until RAM
220 * is initialized
221 */
222 #undef CONFIG_SYS_INIT_RAM_LOCK
223 #define CONFIG_SYS_INIT_RAM_ADDR 0x07d00000 /* unused memory region */
224 #define CONFIG_SYS_INIT_RAM_END 0x4000/* larger space - we have SDRAM initialized */
225
226 #define CONFIG_SYS_GBL_DATA_SIZE 128/* size in bytes reserved for init data */
227 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
228
229 /*-----------------------------------------------------------------------
230 * Start addresses for the final memory configuration
231 * (Set up by the startup code)
232 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
233 */
234
235 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* first 256 MB of SDRAM */
236 #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* next 256MB of SDRAM */
237
238 #define CONFIG_SYS_SDRAM2_BASE 0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
239 #define CONFIG_SYS_SDRAM3_BASE 0x50000000 /* next Non-Cacheable 256MB of SDRAM */
240
241 #define CONFIG_SYS_PCI_PFM_BASE 0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
242
243 #define CONFIG_SYS_PCI_MEM32_BASE 0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
244
245 #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
246
247 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* Base Address of Flash device */
248 #define CONFIG_SYS_FLASH_BASE2 0xfe000000 /* Alternate Flash Base Address */
249
250 #define CONFIG_VERY_BIG_RAM /* we will use up to 256M memory for cause we are short of BATS */
251
252 #define PCI0_IO_BASE_BOOTM 0xfd000000
253
254 #define CONFIG_SYS_RESET_ADDRESS 0x3fffff00
255 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
256 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* u-boot code base */
257 #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
258
259 /* Peripheral Device section */
260
261 /*
262 * Resources on the Tsi108
263 */
264
265 #define CONFIG_SYS_TSI108_CSR_RST_BASE 0xC0000000 /* Tsi108 CSR base after reset */
266 #define CONFIG_SYS_TSI108_CSR_BASE CONFIG_SYS_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
267
268 #define ENABLE_PCI_CSR_BAR /* enables access to Tsi108 CSRs from the PCI/X bus */
269
270 #undef DISABLE_PBM
271
272 /*
273 * PCI stuff
274 *
275 */
276
277 #define CONFIG_PCI /* include pci support */
278 #define CONFIG_TSI108_PCI /* include tsi108 pci support */
279
280 #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
281 #define PCI_HOST_FORCE 1 /* configure as pci host */
282 #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
283
284 #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
285 #define CONFIG_PCI_PNP /* do pci plug-and-play */
286
287 /* PCI MEMORY MAP section */
288
289 /* PCI view of System Memory */
290 #define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
291 #define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
292 #define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
293
294 /* PCI Memory Space */
295 #define CONFIG_SYS_PCI_MEM_BUS (CONFIG_SYS_PCI_MEM_PHYS)
296 #define CONFIG_SYS_PCI_MEM_PHYS (CONFIG_SYS_PCI_MEM32_BASE) /* 0xE0000000 */
297 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256 MB space for PCI/X Mem + SDRAM OCN */
298
299 /* PCI I/O Space */
300 #define CONFIG_SYS_PCI_IO_BUS 0x00000000
301 #define CONFIG_SYS_PCI_IO_PHYS 0xfa000000 /* Changed from fd000000 */
302
303 #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16MB */
304
305 #define _IO_BASE 0x00000000 /* points to PCI I/O space */
306
307 /* PCI Config Space mapping */
308 #define CONFIG_SYS_PCI_CFG_BASE 0xfb000000 /* Changed from FE000000 */
309 #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 /* 16MB */
310
311 #define CONFIG_SYS_IBAT0U 0xFE0003FF
312 #define CONFIG_SYS_IBAT0L 0xFE000002
313
314 #define CONFIG_SYS_IBAT1U 0x00007FFF
315 #define CONFIG_SYS_IBAT1L 0x00000012
316
317 #define CONFIG_SYS_IBAT2U 0x80007FFF
318 #define CONFIG_SYS_IBAT2L 0x80000022
319
320 #define CONFIG_SYS_IBAT3U 0x00000000
321 #define CONFIG_SYS_IBAT3L 0x00000000
322
323 #define CONFIG_SYS_IBAT4U 0x00000000
324 #define CONFIG_SYS_IBAT4L 0x00000000
325
326 #define CONFIG_SYS_IBAT5U 0x00000000
327 #define CONFIG_SYS_IBAT5L 0x00000000
328
329 #define CONFIG_SYS_IBAT6U 0x00000000
330 #define CONFIG_SYS_IBAT6L 0x00000000
331
332 #define CONFIG_SYS_IBAT7U 0x00000000
333 #define CONFIG_SYS_IBAT7L 0x00000000
334
335 #define CONFIG_SYS_DBAT0U 0xE0003FFF
336 #define CONFIG_SYS_DBAT0L 0xE000002A
337
338 #define CONFIG_SYS_DBAT1U 0x00007FFF
339 #define CONFIG_SYS_DBAT1L 0x00000012
340
341 #define CONFIG_SYS_DBAT2U 0x00000000
342 #define CONFIG_SYS_DBAT2L 0x00000000
343
344 #define CONFIG_SYS_DBAT3U 0xC0000003
345 #define CONFIG_SYS_DBAT3L 0xC000002A
346
347 #define CONFIG_SYS_DBAT4U 0x00000000
348 #define CONFIG_SYS_DBAT4L 0x00000000
349
350 #define CONFIG_SYS_DBAT5U 0x00000000
351 #define CONFIG_SYS_DBAT5L 0x00000000
352
353 #define CONFIG_SYS_DBAT6U 0x00000000
354 #define CONFIG_SYS_DBAT6L 0x00000000
355
356 #define CONFIG_SYS_DBAT7U 0x00000000
357 #define CONFIG_SYS_DBAT7L 0x00000000
358
359 /* I2C addresses for the two DIMM SPD chips */
360 #define DIMM0_I2C_ADDR 0x51
361 #define DIMM1_I2C_ADDR 0x52
362
363 /*
364 * For booting Linux, the board info and command line data
365 * have to be in the first 8 MB of memory, since this is
366 * the maximum mapped by the Linux kernel during initialization.
367 */
368 #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
369
370 /*-----------------------------------------------------------------------
371 * FLASH organization
372 */
373 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Flash can be at one of two addresses */
374 #define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */
375 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, /* CONFIG_SYS_FLASH_BASE2 */ }
376
377 #define CONFIG_FLASH_CFI_DRIVER
378 #define CONFIG_SYS_FLASH_CFI
379 #define CONFIG_SYS_WRITE_SWAPPED_DATA
380
381 #define PHYS_FLASH_SIZE 0x01000000
382 #define CONFIG_SYS_MAX_FLASH_SECT (128)
383
384 #define CONFIG_ENV_IS_IN_NVRAM
385 #define CONFIG_ENV_ADDR 0xFC000000
386
387 #define CONFIG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector */
388 #define CONFIG_ENV_SIZE 0x00000400 /* Total Size of Environment Space */
389
390 /*-----------------------------------------------------------------------
391 * Cache Configuration
392 */
393 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
394 #if defined(CONFIG_CMD_KGDB)
395 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
396 #endif
397
398 /*-----------------------------------------------------------------------
399 * L2CR setup -- make sure this is right for your board!
400 * look in include/mpc74xx.h for the defines used here
401 */
402 #undef CONFIG_SYS_L2
403
404 #define L2_INIT 0
405 #define L2_ENABLE (L2_INIT | L2CR_L2E)
406
407 /*
408 * Internal Definitions
409 *
410 * Boot Flags
411 */
412 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
413 #define BOOTFLAG_WARM 0x02 /* Software reboot */
414 #define CONFIG_SYS_SERIAL_HANG_IN_EXCEPTION
415 #endif /* __CONFIG_H */