include/configs/mpc7448hpc2.h

   1 /*
   2  * Copyright (c) 2005 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2006
   5  * Alex Bounine , Tundra Semiconductor Corp.
   6  * Roy Zang     , <tie-fei.zang@freescale.com> Freescale Corp.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board specific configuration options for Freescale
  29  * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
  30  *
  31  */
  32
  33 #ifndef __CONFIG_H
  34 #define __CONFIG_H
  35
  36 /* Board Configuration Definitions */
  37 /* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
  38
  39 #define CONFIG_MPC7448HPC2
  40
  41 #define CONFIG_74xx
  42 #define CONFIG_HIGH_BATS        /* High BATs supported */
  43 #define CONFIG_ALTIVEC          /* undef to disable */
  44
  45 #define CFG_BOARD_NAME          "MPC7448 HPC II"
  46 #define CONFIG_IDENT_STRING     " Freescale MPC7448 HPC II"
  47
  48 #define CFG_OCN_CLK             133000000       /* 133 MHz */
  49 #define CFG_CONFIG_BUS_CLK      133000000
  50
  51 #define CFG_CLK_SPREAD          /* Enable Spread-Spectrum Clock generation */
  52
  53 #undef  CONFIG_ECC              /* disable ECC support */
  54
  55 /* Board-specific Initialization Functions to be called */
  56 #define CFG_BOARD_ASM_INIT
  57 #define CONFIG_BOARD_EARLY_INIT_F
  58 #define CONFIG_BOARD_EARLY_INIT_R
  59 #define CONFIG_MISC_INIT_R
  60
  61 #define CONFIG_HAS_ETH1
  62
  63 #define CONFIG_ENV_OVERWRITE
  64
  65 /*
  66  * High Level Configuration Options
  67  * (easy to change)
  68  */
  69
  70 #define CONFIG_BAUDRATE         115200  /* console baudrate = 115000 */
  71
  72 /*#define CFG_HUSH_PARSER */
  73 #undef CFG_HUSH_PARSER
  74
  75 #define CFG_PROMPT_HUSH_PS2     "> "
  76
  77 /* Pass open firmware flat tree */
  78 #define CONFIG_OF_FLAT_TREE     1
  79 #define CONFIG_OF_BOARD_SETUP   1
  80
  81 #define OF_CPU                  "PowerPC,7448@0"
  82 #define OF_TSI                  "tsi108@c0000000"
  83 #define OF_TBCLK                (bd->bi_busfreq / 8)
  84 #define OF_STDOUT_PATH          "/tsi108@c0000000/serial@7808"
  85
  86 /*
  87  * The following defines let you select what serial you want to use
  88  * for your console driver.
  89  *
  90  * what to do:
  91  * If you have hacked a serial cable onto the second DUART channel,
  92  * change the CFG_DUART port from 1 to 0 below.
  93  *
  94  */
  95
  96 #define CONFIG_CONS_INDEX       1
  97 #define CFG_NS16550
  98 #define CFG_NS16550_SERIAL
  99 #define CFG_NS16550_REG_SIZE    1
 100 #define CFG_NS16550_CLK         CFG_OCN_CLK * 8
 101
 102 #define CFG_NS16550_COM1        (CFG_TSI108_CSR_RST_BASE+0x7808)
 103 #define CFG_NS16550_COM2        (CFG_TSI108_CSR_RST_BASE+0x7C08)
 104 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 105
 106 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds */
 107 #define CONFIG_ZERO_BOOTDELAY_CHECK
 108
 109 #undef CONFIG_BOOTARGS
 110 /* #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" */
 111
 112 #if (CONFIG_BOOTDELAY >= 0)
 113 #define CONFIG_BOOTCOMMAND      "tftpboot 0x400000 zImage.initrd.elf;\
 114  setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
 115  ip=$(ipaddr):$(serverip)$(bootargs_end);  bootm 0x400000; "
 116
 117 #define CONFIG_BOOTARGS "console=ttyS0,115200"
 118 #endif
 119
 120 #undef CONFIG_EXTRA_ENV_SETTINGS
 121
 122 #define CONFIG_SERIAL   "No. 1"
 123
 124 /* Networking Configuration */
 125
 126 #define KSEG1ADDR(a)    (a)     /* Needed by the rtl8139 driver */
 127
 128 #define CONFIG_TSI108_ETH
 129 #define CONFIG_TSI108_ETH_NUM_PORTS     2
 130
 131 #define CONFIG_NET_MULTI
 132
 133 #define CONFIG_BOOTFILE         zImage.initrd.elf
 134 #define CONFIG_LOADADDR         0x400000
 135
 136 /*-------------------------------------------------------------------------- */
 137
 138 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
 139 #define CFG_LOADS_BAUD_CHANGE   /* allow baudrate changes */
 140
 141 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 142
 143 /*
 144  * BOOTP options
 145  */
 146 #define CONFIG_BOOTP_SUBNETMASK
 147 #define CONFIG_BOOTP_GATEWAY
 148 #define CONFIG_BOOTP_HOSTNAME
 149 #define CONFIG_BOOTP_BOOTPATH
 150 #define CONFIG_BOOTP_BOOTFILESIZE
 151
 152
 153 /*
 154  * Command line configuration.
 155  */
 156 #include <config_cmd_default.h>
 157
 158 #define CONFIG_CMD_ASKENV
 159 #define CONFIG_CMD_CACHE
 160 #define CONFIG_CMD_PCI
 161 #define CONFIG_CMD_I2C
 162 #define CONFIG_CMD_SDRAM
 163 #define CONFIG_CMD_EEPROM
 164 #define CONFIG_CMD_FLASH
 165 #define CONFIG_CMD_ENV
 166 #define CONFIG_CMD_BSP
 167 #define CONFIG_CMD_DHCP
 168 #define CONFIG_CMD_PING
 169 #define CONFIG_CMD_DATE
 170
 171
 172 /*set date in u-boot*/
 173 #define CONFIG_RTC_M48T35A
 174 #define CFG_NVRAM_BASE_ADDR     0xfc000000
 175 #define CFG_NVRAM_SIZE          0x8000
 176 /*
 177  * Miscellaneous configurable options
 178  */
 179 #define CONFIG_VERSION_VARIABLE         1
 180 #define CONFIG_TSI108_I2C
 181
 182 #define CFG_I2C_EEPROM_ADDR             0x50    /* I2C EEPROM page 1 */
 183 #define CFG_I2C_EEPROM_ADDR_LEN         1       /* Bytes of address */
 184
 185 #define CFG_LONGHELP            /* undef to save memory */
 186 #define CFG_PROMPT      "=> "   /* Monitor Command Prompt */
 187
 188 #if defined(CONFIG_CMD_KGDB)
 189 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size */
 190 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 191 #else
 192 #define CFG_CBSIZE              256     /* Console I/O Buffer Size */
 193 #endif
 194
 195 #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)/* Print Buffer Size */
 196 #define CFG_MAXARGS     16              /* max number of command args */
 197 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 198
 199 #define CFG_MEMTEST_START       0x00400000      /* memtest works on */
 200 #define CFG_MEMTEST_END         0x07c00000      /* 4 ... 124 MB in DRAM */
 201
 202 #define CFG_LOAD_ADDR   0x00400000      /* default load address */
 203
 204 #define CFG_HZ          1000            /* decr freq: 1ms ticks */
 205
 206 /*
 207  * Low Level Configuration Settings
 208  * (address mappings, register initial values, etc.)
 209  * You should know what you are doing if you make changes here.
 210  */
 211
 212 /*-----------------------------------------------------------------------
 213  * Definitions for initial stack pointer and data area
 214  */
 215
 216 /*
 217  * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
 218  * To an unused memory region. The stack will remain in cache until RAM
 219  * is initialized
 220  */
 221 #undef  CFG_INIT_RAM_LOCK
 222 #define CFG_INIT_RAM_ADDR       0x07d00000      /* unused memory region */
 223 #define CFG_INIT_RAM_END        0x4000/* larger space - we have SDRAM initialized */
 224
 225 #define CFG_GBL_DATA_SIZE       128/* size in bytes reserved for init data */
 226 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 227
 228 /*-----------------------------------------------------------------------
 229  * Start addresses for the final memory configuration
 230  * (Set up by the startup code)
 231  * Please note that CFG_SDRAM_BASE _must_ start at 0
 232  */
 233
 234 #define CFG_SDRAM_BASE          0x00000000      /* first 256 MB of SDRAM */
 235 #define CFG_SDRAM1_BASE         0x10000000      /* next 256MB of SDRAM */
 236
 237 #define CFG_SDRAM2_BASE 0x40000000      /* beginning of non-cacheable alias for SDRAM - first 256MB */
 238 #define CFG_SDRAM3_BASE 0x50000000      /* next Non-Cacheable 256MB of SDRAM */
 239
 240 #define CFG_PCI_PFM_BASE        0x80000000      /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
 241
 242 #define CFG_PCI_MEM32_BASE      0xE0000000      /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
 243
 244 #define CFG_MISC_REGION_BASE    0xf0000000      /* Base Address for (PCI/X + Flash) region */
 245
 246 #define CFG_FLASH_BASE  0xff000000      /* Base Address of Flash device */
 247 #define CFG_FLASH_BASE2 0xfe000000      /* Alternate Flash Base Address */
 248
 249 #define CONFIG_VERY_BIG_RAM     /* we will use up to 256M memory for cause we are short of BATS */
 250
 251 #define PCI0_IO_BASE_BOOTM      0xfd000000
 252
 253 #define CFG_RESET_ADDRESS       0x3fffff00
 254 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 255 #define CFG_MONITOR_BASE        TEXT_BASE       /* u-boot code base */
 256 #define CFG_MALLOC_LEN          (256 << 10)     /* Reserve 256 kB for malloc */
 257
 258 /* Peripheral Device section */
 259
 260 /*
 261  * Resources on the Tsi108
 262  */
 263
 264 #define CFG_TSI108_CSR_RST_BASE 0xC0000000      /* Tsi108 CSR base after reset */
 265 #define CFG_TSI108_CSR_BASE     CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
 266
 267 #define ENABLE_PCI_CSR_BAR      /* enables access to Tsi108 CSRs from the PCI/X bus */
 268
 269 #undef  DISABLE_PBM
 270
 271 /*
 272  * PCI stuff
 273  *
 274  */
 275
 276 #define CONFIG_PCI              /* include pci support */
 277 #define CONFIG_TSI108_PCI       /* include tsi108 pci support */
 278
 279 #define PCI_HOST_ADAPTER        0       /* configure as pci adapter */
 280 #define PCI_HOST_FORCE          1       /* configure as pci host */
 281 #define PCI_HOST_AUTO           2       /* detected via arbiter enable */
 282
 283 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function */
 284 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 285
 286 /* PCI MEMORY MAP section */
 287
 288 /* PCI view of System Memory */
 289 #define CFG_PCI_MEMORY_BUS      0x00000000
 290 #define CFG_PCI_MEMORY_PHYS     0x00000000
 291 #define CFG_PCI_MEMORY_SIZE     0x80000000
 292
 293 /* PCI Memory Space */
 294 #define CFG_PCI_MEM_BUS         (CFG_PCI_MEM_PHYS)
 295 #define CFG_PCI_MEM_PHYS        (CFG_PCI_MEM32_BASE)    /* 0xE0000000 */
 296 #define CFG_PCI_MEM_SIZE        0x10000000      /* 256 MB space for PCI/X Mem + SDRAM OCN */
 297
 298 /* PCI I/O Space */
 299 #define CFG_PCI_IO_BUS          0x00000000
 300 #define CFG_PCI_IO_PHYS         0xfa000000      /* Changed from fd000000 */
 301
 302 #define CFG_PCI_IO_SIZE         0x01000000      /* 16MB */
 303
 304 #define _IO_BASE                0x00000000      /* points to PCI I/O space      */
 305
 306 /* PCI Config Space mapping */
 307 #define CFG_PCI_CFG_BASE        0xfb000000      /* Changed from FE000000 */
 308 #define CFG_PCI_CFG_SIZE        0x01000000      /* 16MB */
 309
 310 #define CFG_IBAT0U      0xFE0003FF
 311 #define CFG_IBAT0L      0xFE000002
 312
 313 #define CFG_IBAT1U      0x00007FFF
 314 #define CFG_IBAT1L      0x00000012
 315
 316 #define CFG_IBAT2U      0x80007FFF
 317 #define CFG_IBAT2L      0x80000022
 318
 319 #define CFG_IBAT3U      0x00000000
 320 #define CFG_IBAT3L      0x00000000
 321
 322 #define CFG_IBAT4U      0x00000000
 323 #define CFG_IBAT4L      0x00000000
 324
 325 #define CFG_IBAT5U      0x00000000
 326 #define CFG_IBAT5L      0x00000000
 327
 328 #define CFG_IBAT6U      0x00000000
 329 #define CFG_IBAT6L      0x00000000
 330
 331 #define CFG_IBAT7U      0x00000000
 332 #define CFG_IBAT7L      0x00000000
 333
 334 #define CFG_DBAT0U      0xE0003FFF
 335 #define CFG_DBAT0L      0xE000002A
 336
 337 #define CFG_DBAT1U      0x00007FFF
 338 #define CFG_DBAT1L      0x00000012
 339
 340 #define CFG_DBAT2U      0x00000000
 341 #define CFG_DBAT2L      0x00000000
 342
 343 #define CFG_DBAT3U      0xC0000003
 344 #define CFG_DBAT3L      0xC000002A
 345
 346 #define CFG_DBAT4U      0x00000000
 347 #define CFG_DBAT4L      0x00000000
 348
 349 #define CFG_DBAT5U      0x00000000
 350 #define CFG_DBAT5L      0x00000000
 351
 352 #define CFG_DBAT6U      0x00000000
 353 #define CFG_DBAT6L      0x00000000
 354
 355 #define CFG_DBAT7U      0x00000000
 356 #define CFG_DBAT7L      0x00000000
 357
 358 /* I2C addresses for the two DIMM SPD chips */
 359 #define DIMM0_I2C_ADDR  0x51
 360 #define DIMM1_I2C_ADDR  0x52
 361
 362 /*
 363  * For booting Linux, the board info and command line data
 364  * have to be in the first 8 MB of memory, since this is
 365  * the maximum mapped by the Linux kernel during initialization.
 366  */
 367 #define CFG_BOOTMAPSZ   (8<<20) /* Initial Memory map for Linux */
 368
 369 /*-----------------------------------------------------------------------
 370  * FLASH organization
 371  */
 372 #define CFG_MAX_FLASH_BANKS     1               /* Flash can be at one of two addresses */
 373 #define FLASH_BANK_SIZE         0x01000000      /* 16 MB Total */
 374 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE, /* CFG_FLASH_BASE2 */ }
 375
 376 #define CFG_FLASH_CFI_DRIVER
 377 #define CFG_FLASH_CFI
 378 #define CFG_WRITE_SWAPPED_DATA
 379
 380 #define PHYS_FLASH_SIZE         0x01000000
 381 #define CFG_MAX_FLASH_SECT      (128)
 382
 383 #define CFG_ENV_IS_IN_NVRAM
 384 #define CFG_ENV_ADDR            0xFC000000
 385
 386 #define CFG_ENV_OFFSET  0x00000000      /* Offset of Environment Sector */
 387 #define CFG_ENV_SIZE    0x00000400      /* Total Size of Environment Space */
 388
 389 /*-----------------------------------------------------------------------
 390  * Cache Configuration
 391  */
 392 #define CFG_CACHELINE_SIZE      32      /* For all MPC74xx CPUs */
 393 #if defined(CONFIG_CMD_KGDB)
 394 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 395 #endif
 396
 397 /*-----------------------------------------------------------------------
 398  * L2CR setup -- make sure this is right for your board!
 399  * look in include/mpc74xx.h for the defines used here
 400  */
 401 #undef CFG_L2
 402
 403 #define L2_INIT         0
 404 #define L2_ENABLE       (L2_INIT | L2CR_L2E)
 405
 406 /*
 407  * Internal Definitions
 408  *
 409  * Boot Flags
 410  */
 411 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH */
 412 #define BOOTFLAG_WARM   0x02    /* Software reboot */
 413 #define CFG_SERIAL_HANG_IN_EXCEPTION
 414 #endif  /* __CONFIG_H */