include/configs/mpc7448hpc2.h

   1 /*
   2  * Copyright (c) 2005 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2006
   5  * Alex Bounine , Tundra Semiconductor Corp.
   6  * Roy Zang     , Freescale Corp.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /****************************************************************
  28  *
  29  * board specific configuration options for Freescale
  30  * MPC7448HPC2 (High-Performance Computing II) (Taiga) board
  31  *
  32  ****************************************************************/
  33
  34 #ifndef __CONFIG_H
  35 #define __CONFIG_H
  36
  37 #undef DEBUG
  38
  39 /* Board Configuration Definitions */
  40 /* MPC7448HPC2 (High-Performance Computing II) (Taiga) board */
  41
  42 #define CONFIG_MPC7448HPC2
  43
  44 #define CONFIG_74xx
  45 #define CONFIG_750FX            /* this option to enable init of extended BATs */
  46 #define CONFIG_ALTIVEC          /* undef to disable */
  47
  48 #define CFG_BOARD_NAME       "MPC7448 HPC II"
  49 #define CONFIG_IDENT_STRING  " Freescale MPC7448 HPC II"
  50
  51 #define CFG_OCN_CLK         133000000   /* 133 MHz */
  52 #define CFG_CONFIG_BUS_CLK         133000000
  53
  54 #define CFG_CLK_SPREAD          /* Enable Spread-Spectrum Clock generation */
  55
  56 #undef  CONFIG_ECC              /* disable ECC support */
  57
  58 /* Board-specific Initialization Functions to be called */
  59 #define CFG_BOARD_ASM_INIT
  60 #define CONFIG_BOARD_EARLY_INIT_F
  61 #define CONFIG_BOARD_EARLY_INIT_R
  62 #define CONFIG_MISC_INIT_R
  63
  64 /* Default MAC Addresses for on-chip GIGE Controller */
  65
  66 #define CONFIG_ETHADDR      00:06:D2:00:00:01
  67
  68 #define CONFIG_HAS_ETH1
  69 #define CONFIG_ETH1ADDR     00:06:D2:00:00:02
  70
  71 #define CONFIG_ENV_OVERWRITE
  72
  73 /*
  74  * High Level Configuration Options
  75  * (easy to change)
  76  */
  77
  78 #define CONFIG_BAUDRATE    115200       /* console baudrate = 115000 */
  79
  80 /*#define CFG_HUSH_PARSER */
  81 #undef CFG_HUSH_PARSER
  82
  83 #define CFG_PROMPT_HUSH_PS2  "> "
  84
  85 /* Pass open firmware flat tree */
  86 #define CONFIG_OF_FLAT_TREE     1
  87 #define CONFIG_OF_BOARD_SETUP   1
  88
  89 /* maximum size of the flat tree (8K) */
  90 #define OF_FLAT_TREE_MAX_SIZE   8192
  91
  92 #define OF_CPU                  "PowerPC,7448@0"
  93 #define OF_TSI                  "tsi108@c0000000"
  94 #define OF_TBCLK                (bd->bi_busfreq / 8)
  95 #define OF_STDOUT_PATH          "/tsi108@c0000000/serial@7808"
  96
  97 /*
  98  * The following defines let you select what serial you want to use
  99  * for your console driver.
 100  *
 101  * what to do:
 102  * If you have hacked a serial cable onto the second DUART channel, change the CFG_DUART port from 1
 103  * to 0 below.
 104  *
 105  */
 106
 107 #define CONFIG_CONS_INDEX     1
 108 #define CFG_NS16550
 109 #define CFG_NS16550_SERIAL
 110 #define CFG_NS16550_REG_SIZE    1
 111 #define CFG_NS16550_CLK         CFG_OCN_CLK * 8
 112
 113 #define CFG_NS16550_COM1        (CFG_TSI108_CSR_RST_BASE+0x7808)
 114 #define CFG_NS16550_COM2        (CFG_TSI108_CSR_RST_BASE+0x7C08)
 115 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 116
 117 #define CONFIG_BOOTDELAY     3  /* autoboot after 3 seconds */
 118 #define CONFIG_ZERO_BOOTDELAY_CHECK
 119
 120 #undef CONFIG_BOOTARGS
 121 /*#define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" */
 122
 123 #if (CONFIG_BOOTDELAY >= 0)
 124 #define CONFIG_BOOTCOMMAND      "tftpboot 0x400000 zImage.initrd.elf;\
 125  setenv bootargs $(bootargs) $(bootargs_root) nfsroot=$(serverip):$(rootpath) \
 126  ip=$(ipaddr):$(serverip)$(bootargs_end);  bootm 0x400000; "
 127
 128 #define CONFIG_BOOTARGS "console=ttyS0,115200"
 129 #endif
 130
 131 #undef CONFIG_EXTRA_ENV_SETTINGS
 132
 133 #define CONFIG_SERIAL    "No. 1"
 134
 135 /* Networking Configuration */
 136
 137 #define KSEG1ADDR(a)   (a)      /* Needed by the rtl8139 driver */
 138
 139 #define CONFIG_TSI108_ETH
 140 #define CONFIG_TSI108_ETH_NUM_PORTS 2
 141
 142 #define CONFIG_NET_MULTI
 143
 144 #define CONFIG_IPADDR       172.27.234.48
 145 #define CONFIG_SERVERIP     172.27.234.10
 146 #define CONFIG_NETMASK      255.255.0.0
 147 #define CONFIG_GATEWAYIP    172.27.255.254
 148
 149 #define CONFIG_BOOTFILE     zImage.initrd.elf
 150 #define CONFIG_LOADADDR     0x400000
 151
 152 /*-------------------------------------------------------------------------- */
 153
 154 #define CONFIG_LOADS_ECHO   0   /* echo off for serial download */
 155 #define CFG_LOADS_BAUD_CHANGE   /* allow baudrate changes */
 156
 157 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 158
 159 #define CONFIG_BOOTP_MASK  (CONFIG_BOOTP_DEFAULT | \
 160                             CONFIG_BOOTP_BOOTFILESIZE)
 161
 162 #define CONFIG_COMMANDS (CONFIG_CMD_DFL \
 163                 | CFG_CMD_ASKENV \
 164                 | CFG_CMD_CACHE \
 165                 | CFG_CMD_PCI \
 166                 | CFG_CMD_I2C \
 167                 | CFG_CMD_SDRAM \
 168                 | CFG_CMD_EEPROM \
 169                 | CFG_CMD_FLASH \
 170                 | CFG_CMD_ENV \
 171                 | CFG_CMD_BSP \
 172                 | CFG_CMD_DHCP \
 173                 | CFG_CMD_PING \
 174                 | CFG_CMD_DATE)
 175
 176 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 177 #include <cmd_confdefs.h>
 178
 179 /*set date in u-boot*/
 180 #define CONFIG_RTC_M48T35A
 181 #define CFG_NVRAM_BASE_ADDR 0xfc000000
 182 #define CFG_NVRAM_SIZE 0x8000
 183 /*
 184  * Miscellaneous configurable options
 185  */
 186 #define CONFIG_VERSION_VARIABLE 1
 187 #define CONFIG_TSI108_I2C
 188
 189 #define CFG_I2C_EEPROM_ADDR      0x50   /* I2C EEPROM page 1 */
 190 #define CFG_I2C_EEPROM_ADDR_LEN     1   /* Bytes of address */
 191
 192 #define CFG_LONGHELP            /* undef to save memory */
 193 #define CFG_PROMPT      "=> "   /* Monitor Command Prompt */
 194
 195 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 196 #define CFG_CBSIZE               1024   /* Console I/O Buffer Size */
 197 #define CONFIG_KGDB_BAUDRATE   115200   /* speed to run kgdb serial port at */
 198 #else
 199 #define CFG_CBSIZE               256    /* Console I/O Buffer Size */
 200 #endif
 201
 202 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 203 #define CFG_MAXARGS     16      /* max number of command args */
 204 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size */
 205
 206 /*
 207 #define CFG_DRAM_TEST
 208  * DRAM tests
 209  *   CFG_DRAM_TEST - enables the following tests.
 210  *
 211  *   CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
 212  *                        Environment variable 'test_dram_data' must be
 213  *                        set to 'y'.
 214  *   CFG_DRAM_TEST_ADDRESS - Enables test to verify that each word is uniquely
 215  *                        addressable. Environment variable
 216  *                        'test_dram_address' must be set to 'y'.
 217  *   CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
 218  *                        This test takes about 6 minutes to test 64 MB.
 219  *                        Environment variable 'test_dram_walk' must be
 220  *                        set to 'y'.
 221  */
 222 #undef CFG_DRAM_TEST
 223 #define CFG_MEMTEST_START       0x00400000      /* memtest works on */
 224 #define CFG_MEMTEST_END         0x07c00000      /* 4 ... 124 MB in DRAM */
 225 #if defined(CFG_DRAM_TEST)
 226 #define CFG_DRAM_TEST_DATA
 227 #define CFG_DRAM_TEST_ADDRESS
 228 #define CFG_DRAM_TEST_WALK
 229 #endif                          /* CFG_DRAM_TEST */
 230
 231 #define CFG_LOAD_ADDR           0x00400000      /* default load address */
 232
 233 #define CFG_HZ                  1000    /* decr freq: 1ms ticks */
 234
 235 /*
 236  * Low Level Configuration Settings
 237  * (address mappings, register initial values, etc.)
 238  * You should know what you are doing if you make changes here.
 239  */
 240
 241 /*-----------------------------------------------------------------------
 242  * Definitions for initial stack pointer and data area
 243  */
 244
 245 /*
 246  * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
 247  * To an unused memory region. The stack will remain in cache until RAM
 248  * is initialized
 249 */
 250 #undef  CFG_INIT_RAM_LOCK
 251 #define CFG_INIT_RAM_ADDR   0x07d00000  /* unused memory region */
 252 #define CFG_INIT_RAM_END 0x4000 /* larger space - we have SDRAM initialized */
 253
 254 #define CFG_GBL_DATA_SIZE   128 /* size in bytes reserved for init data */
 255 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 256
 257 /*-----------------------------------------------------------------------
 258  * Start addresses for the final memory configuration
 259  * (Set up by the startup code)
 260  * Please note that CFG_SDRAM_BASE _must_ start at 0
 261  */
 262
 263 #define CFG_SDRAM_BASE       0x00000000 /* first 256 MB of SDRAM */
 264 #define CFG_SDRAM1_BASE      0x10000000 /* next 256MB of SDRAM */
 265
 266 #define CFG_SDRAM2_BASE      0x40000000 /* beginning of non-cacheable alias for SDRAM - first 256MB */
 267 #define CFG_SDRAM3_BASE      0x50000000 /* next Non-Cacheable 256MB of SDRAM */
 268
 269 #define CFG_PCI_PFM_BASE     0x80000000 /* Prefetchable (cacheable) PCI/X PFM and SDRAM OCN (128MB+128MB) */
 270
 271 #define CFG_PCI_MEM32_BASE   0xE0000000 /* Non-Cacheable PCI/X MEM and SDRAM OCN (128MB+128MB) */
 272
 273 #define CFG_MISC_REGION_BASE 0xf0000000 /* Base Address for (PCI/X + Flash) region */
 274
 275 #define CFG_FLASH_BASE       0xff000000 /* Base Address of Flash device */
 276 #define CFG_FLASH_BASE2      0xfe000000 /* Alternate Flash Base Address */
 277
 278 #define CONFIG_VERY_BIG_RAM     /* we will use up to 256M memory for cause we are short of BATS */
 279
 280 #define PCI0_IO_BASE_BOOTM   0xfd000000
 281
 282 #define CFG_RESET_ADDRESS  0x3fffff00
 283 #define CFG_MONITOR_LEN    (256 << 10)  /* Reserve 256 kB for Monitor */
 284 #define CFG_MONITOR_BASE   TEXT_BASE    /* u-boot code base */
 285 #define CFG_MALLOC_LEN     (256 << 10)  /* Reserve 256 kB for malloc */
 286
 287 /* Peripheral Device section */
 288
 289 /*******************************************************
 290  * Resources on the Tsi108
 291  *******************************************************/
 292
 293 #define CFG_TSI108_CSR_RST_BASE 0xC0000000      /* Tsi108 CSR base after reset */
 294 #define CFG_TSI108_CSR_BASE     CFG_TSI108_CSR_RST_BASE /* Runtime Tsi108 CSR base */
 295
 296 #define ENABLE_PCI_CSR_BAR      /* enables access to Tsi108 CSRs from the PCI/X bus */
 297
 298 #undef  DISABLE_PBM
 299
 300 /*-----------------------------------------------------------------------
 301  * PCI stuff
 302  *-----------------------------------------------------------------------
 303  */
 304
 305 #define CONFIG_PCI              /* include pci support */
 306 #define CONFIG_TSI108_PCI       /* include tsi108 pci support */
 307
 308 #define PCI_HOST_ADAPTER  0     /* configure as pci adapter */
 309 #define PCI_HOST_FORCE    1     /* configure as pci host */
 310 #define PCI_HOST_AUTO     2     /* detected via arbiter enable */
 311
 312 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function */
 313 #define CONFIG_PCI_PNP          /* do pci plug-and-play */
 314
 315 /* PCI MEMORY MAP section */
 316
 317 /* PCI view of System Memory */
 318 #define CFG_PCI_MEMORY_BUS      0x00000000
 319 #define CFG_PCI_MEMORY_PHYS     0x00000000
 320 #define CFG_PCI_MEMORY_SIZE     0x80000000
 321
 322 /* PCI Memory Space */
 323 #define CFG_PCI_MEM_BUS         (CFG_PCI_MEM_PHYS)
 324 #define CFG_PCI_MEM_PHYS        (CFG_PCI_MEM32_BASE)    //CFG_PCI_MEM32_BASE = 0xE0000000
 325 #define CFG_PCI_MEM_SIZE        0x10000000      /* 256 MB space for PCI/X Mem + SDRAM OCN */
 326
 327 /* PCI I/O Space */
 328 #define CFG_PCI_IO_BUS          0x00000000
 329 #define CFG_PCI_IO_PHYS         0xfa000000      /* Changed from fd000000 */
 330
 331 #define CFG_PCI_IO_SIZE         0x01000000      /* 16MB */
 332
 333 #define _IO_BASE                0x00000000      /* points to PCI I/O space      */
 334
 335 /* PCI Config Space mapping */
 336 #define CFG_PCI_CFG_BASE        0xfb000000      /* Changed from FE000000 */
 337 #define CFG_PCI_CFG_SIZE        0x01000000      /* 16MB */
 338
 339 #define CFG_IBAT0U  0xFE0003FF
 340 #define CFG_IBAT0L  0xFE000002
 341
 342 #define CFG_IBAT1U  0x00007FFF
 343 #define CFG_IBAT1L  0x00000012
 344
 345 #define CFG_IBAT2U  0x80007FFF
 346 #define CFG_IBAT2L  0x80000022
 347
 348 #define CFG_IBAT3U  0x00000000
 349 #define CFG_IBAT3L  0x00000000
 350
 351 #define CFG_IBAT4U  0x00000000
 352 #define CFG_IBAT4L  0x00000000
 353
 354 #define CFG_IBAT5U  0x00000000
 355 #define CFG_IBAT5L  0x00000000
 356
 357 #define CFG_IBAT6U  0x00000000
 358 #define CFG_IBAT6L  0x00000000
 359
 360 #define CFG_IBAT7U  0x00000000
 361 #define CFG_IBAT7L  0x00000000
 362
 363 #define CFG_DBAT0U  0xE0003FFF
 364 #define CFG_DBAT0L  0xE000002A
 365
 366 #define CFG_DBAT1U  0x00007FFF
 367 #define CFG_DBAT1L  0x00000012
 368
 369 #define CFG_DBAT2U  0x00000000
 370 #define CFG_DBAT2L  0x00000000
 371
 372 #define CFG_DBAT3U  0xC0000003
 373 #define CFG_DBAT3L  0xC000002A
 374
 375 #define CFG_DBAT4U  0x00000000
 376 #define CFG_DBAT4L  0x00000000
 377
 378 #define CFG_DBAT5U  0x00000000
 379 #define CFG_DBAT5L  0x00000000
 380
 381 #define CFG_DBAT6U  0x00000000
 382 #define CFG_DBAT6L  0x00000000
 383
 384 #define CFG_DBAT7U  0x00000000
 385 #define CFG_DBAT7L  0x00000000
 386
 387 /* I2C addresses for the two DIMM SPD chips */
 388 #define DIMM0_I2C_ADDR    0x51
 389 #define DIMM1_I2C_ADDR    0x52
 390
 391 /*
 392  * For booting Linux, the board info and command line data
 393  * have to be in the first 8 MB of memory, since this is
 394  * the maximum mapped by the Linux kernel during initialization.
 395  */
 396 #define CFG_BOOTMAPSZ    (8<<20)        /* Initial Memory map for Linux */
 397
 398 /*-----------------------------------------------------------------------
 399  * FLASH organization
 400  */
 401 #define CFG_MAX_FLASH_BANKS  1  /* Flash can be at one of two addresses */
 402 #define FLASH_BANK_SIZE      0x01000000 /* 16 MB Total */
 403 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE, CFG_FLASH_BASE2}
 404
 405 #define CFG_FLASH_CFI_DRIVER
 406 #define CFG_FLASH_CFI
 407 #define CFG_FLASH_CFI_SWAP
 408
 409 #define PHYS_FLASH_SIZE     0x01000000
 410 #define CFG_MAX_FLASH_SECT  (128)
 411
 412 #define CFG_ENV_IS_IN_NVRAM
 413 #define CFG_ENV_ADDR         0xFC000000
 414
 415 #define CFG_ENV_OFFSET      0x00000000  /* Offset of Environment Sector */
 416 #define CFG_ENV_SIZE        0x00000400  /* Total Size of Environment Space */
 417
 418 /*-----------------------------------------------------------------------
 419  * Cache Configuration
 420  */
 421 #define CFG_CACHELINE_SIZE   32 /* For all MPC74xx CPUs */
 422 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 423 #define CFG_CACHELINE_SHIFT   5 /* log base 2 of the above value */
 424 #endif
 425
 426 /*-----------------------------------------------------------------------
 427  * L2CR setup -- make sure this is right for your board!
 428  * look in include/mpc74xx.h for the defines used here
 429  */
 430 #undef CFG_L2
 431
 432 #define L2_INIT  0
 433 #define L2_ENABLE  (L2_INIT | L2CR_L2E)
 434
 435 /*
 436  * Internal Definitions
 437  *
 438  * Boot Flags
 439  */
 440 #define BOOTFLAG_COLD    0x01   /* Normal Power-On: Boot from FLASH */
 441 #define BOOTFLAG_WARM    0x02   /* Software reboot */
 442 #define CFG_EXCEPTION_AFTER_RELOCATE
 443 #define CFG_SERIAL_HANG_IN_EXCEPTION
 444 #endif                          /* __CONFIG_H */