include/configs/o2dnt-common.h

   1 /*
   2  *  Common configuration options for ifm camera boards
   3  *
   4  * (C) Copyright 2005
   5  * Sebastien Cazaux, ifm electronic gmbh
   6  *
   7  * (C) Copyright 2012
   8  * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __O2D_CONFIG_H
  14 #define __O2D_CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_MPC5200
  20
  21 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* running at 33.000000MHz */
  22
  23 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
  24 #if defined(CONFIG_CMD_KGDB)
  25 /* log base 2 of the above value */
  26 #define CONFIG_SYS_CACHELINE_SHIFT      5
  27 #endif
  28
  29 /*
  30 #define CONFIG_POST     (CONFIG_SYS_POST_MEMORY | \
  31                          CONFIG_SYS_POST_I2C)
  32 */
  33
  34 #ifdef CONFIG_POST
  35 /* preserve space for the post_word at end of on-chip SRAM */
  36 #define MPC5XXX_SRAM_POST_SIZE  (MPC5XXX_SRAM_SIZE - 4)
  37 #endif
  38
  39 /*
  40  * Serial console configuration
  41  */
  42 #define CONFIG_PSC_CONSOLE      5       /* console is on PSC5 */
  43 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  44 #define CONFIG_SYS_BAUDRATE_TABLE \
  45         { 9600, 19200, 38400, 57600, 115200, 230400 }
  46
  47 /*
  48  * PCI Mapping:
  49  * 0x40000000 - 0x4fffffff - PCI Memory
  50  * 0x50000000 - 0x50ffffff - PCI IO Space
  51  */
  52
  53 #define CONFIG_PCI_MEM_BUS      0x40000000
  54 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  55 #define CONFIG_PCI_MEM_SIZE     0x10000000
  56
  57 #define CONFIG_PCI_IO_BUS       0x50000000
  58 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  59 #define CONFIG_PCI_IO_SIZE      0x01000000
  60
  61 #define CONFIG_SYS_XLB_PIPELINING       1
  62
  63 /* Partitions */
  64 #define CONFIG_ISO_PARTITION
  65
  66 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  67
  68 #define CONFIG_SYS_ALT_MEMTEST  /* Much more complex memory test */
  69
  70 /*
  71  * Supported commands
  72  */
  73 #define CONFIG_CMD_EEPROM
  74 #ifdef CONFIG_PCI
  75 #define CONFIG_CMD_PCI
  76 #endif
  77 #ifdef CONFIG_POST
  78 #define CONFIG_CMD_DIAG
  79 #endif
  80
  81 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
  82 /* Boot low with 16 or 32 MB Flash */
  83 #define CONFIG_SYS_LOWBOOT      1
  84 #elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
  85 #error "CONFIG_SYS_TEXT_BASE value is invalid"
  86 #endif
  87
  88
  89 #define CONFIG_PREBOOT  "run master"
  90
  91 #undef  CONFIG_BOOTARGS
  92
  93 #if !defined(CONSOLE_DEV)
  94 #define CONSOLE_DEV     "ttyPSC1"
  95 #endif
  96
  97 /*
  98  * Default environment for booting old and new kernel versions
  99  */
 100 #define CONFIG_IFM_DEFAULT_ENV_OLD                                      \
 101         "flash_self_old=run ramargs addip addmem;"                      \
 102                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 103         "flash_nfs_old=run nfsargs addip addmem;"                       \
 104                 "bootm ${kernel_addr}\0"                                \
 105         "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"                \
 106                 "run nfsargs addip addmem;"                             \
 107                 "bootm ${kernel_addr_r}\0"
 108
 109 #define CONFIG_IFM_DEFAULT_ENV_NEW                                      \
 110         "fdt_addr_r=900000\0"                                           \
 111         "fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0"        \
 112         "flash_self=run ramargs addip addtty addmisc;"                  \
 113                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 114         "flash_nfs=run nfsargs addip addtty addmisc;"                   \
 115                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 116         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
 117                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 118                 "run nfsargs addip addtty addmisc;"                     \
 119                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 120
 121 #define CONFIG_IFM_DEFAULT_ENV_SETTINGS                                 \
 122         "IOpin=0x64\0"                                                  \
 123         "addip=setenv bootargs ${bootargs} "                            \
 124                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 125                 ":${hostname}:${netdev}:off panic=1\0"                  \
 126         "addmem=setenv bootargs ${bootargs} ${memlimit}\0"              \
 127         "addmisc=sete bootargs ${bootargs} ${miscargs}\0"               \
 128         "addtty=sete bootargs ${bootargs} console="                     \
 129                 CONSOLE_DEV ",${baudrate}\0"                    \
 130         "bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \
 131         "kernel_addr_r=600000\0"                                        \
 132         "initrd_high=0x03e00000\0"                                      \
 133         "memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0"                      \
 134         "memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
 135         "netdev=eth0\0"                                                 \
 136         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 137                 "nfsroot=${serverip}:${rootpath}\0"                     \
 138         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 139         "linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
 140         "progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
 141                 "cp.b ${fileaddr} ${linbot} ${filesize}\0"              \
 142         "ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
 143         "progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};"     \
 144                 "cp.b ${fileaddr} ${rambot} ${filesize}\0"              \
 145         "jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0"  \
 146         "progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};"     \
 147                 "cp.b ${fileaddr} ${jffbot} ${filesize}\0"              \
 148         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 149         "uboname=" CONFIG_BOARD_NAME                                    \
 150                 "/u-boot.bin_" CONFIG_BOARD_NAME "_act\0"               \
 151         "progubo=tftp 200000 ${uboname};"                               \
 152                 "protect off ${ubobot} ${ubotop};"                      \
 153                 "erase ${ubobot} ${ubotop};"                            \
 154                 "cp.b ${fileaddr} ${ubobot} ${filesize}\0"              \
 155         "unlock=yes\0"                                                  \
 156         "post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;"     \
 157                 "setenv bootdelay 1;"                                   \
 158                 "crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" "            \
 159                         BOARD_POST_CRC32_END";"                         \
 160                 "setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
 161
 162 #define CONFIG_BOOTCOMMAND      "run post"
 163
 164 /*
 165  * IPB Bus clocking configuration.
 166  */
 167 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 168
 169 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 170 /*
 171  * PCI Bus clocking configuration
 172  *
 173  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 174  * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 175  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 176  */
 177 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2    /* define for 66MHz speed */
 178 #endif
 179
 180 /*
 181  * I2C configuration
 182  */
 183 #define CONFIG_HARD_I2C                 1       /* I2C with hardware support */
 184 #define CONFIG_SYS_I2C_MODULE           1       /* Select I2C module #1 or #2 */
 185 #define CONFIG_SYS_I2C_SPEED            100000  /* 100 kHz */
 186 #define CONFIG_SYS_I2C_SLAVE            0x7F
 187
 188 /*
 189  * EEPROM configuration:
 190  *
 191  * O2DNT board is equiped with Ramtron FRAM device FM24CL16
 192  * 16 Kib Ferroelectric Nonvolatile serial RAM memory
 193  * organized as 2048 x 8 bits and addressable as eight I2C devices
 194  * 0x50 ... 0x57 each 256 bytes in size
 195  *
 196  */
 197 #define CONFIG_SYS_I2C_FRAM
 198 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 199 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 200 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 201 /*
 202  * There is no write delay with FRAM, write operations are performed at bus
 203  * speed. Thus, no status polling or write delay is needed.
 204  */
 205
 206 /*
 207  * Flash configuration
 208  */
 209 #define CONFIG_SYS_FLASH_CFI            1
 210 #define CONFIG_FLASH_CFI_DRIVER         1
 211 #define CONFIG_FLASH_16BIT
 212 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 213 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
 214 #define CONFIG_SYS_FLASH_EMPTY_INFO
 215
 216 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 217 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 218 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Erase Timeout (in ms) */
 219 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Write Timeout (in ms) */
 220 /* Timeout for Flash Clear Lock Bits (in ms) */
 221 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    10000
 222 /* "Real" (hardware) sectors protection */
 223 #define CONFIG_SYS_FLASH_PROTECTION
 224
 225 /*
 226  * Environment settings
 227  */
 228 #define CONFIG_ENV_IS_IN_FLASH  1
 229 #define CONFIG_ENV_SIZE         0x20000
 230 #define CONFIG_ENV_SECT_SIZE    0x20000
 231 #define CONFIG_ENV_OVERWRITE    1
 232 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00040000)
 233
 234 /*
 235  * Memory map
 236  */
 237 #define CONFIG_SYS_MBAR         0xF0000000
 238 #define CONFIG_SYS_SDRAM_BASE   0x00000000
 239 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 240
 241 /* Use SRAM until RAM will be available */
 242 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 243 #ifdef CONFIG_POST
 244 /* preserve space for the post_word at end of on-chip SRAM */
 245 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 246 #else
 247 /* End of used area in DPRAM */
 248 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 249 #endif
 250
 251 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 252                                          GENERATED_GBL_DATA_SIZE)
 253 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 254
 255 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 256 #define CONFIG_SYS_MONITOR_LEN          (192 << 10) /* 192 kB for Monitor */
 257 #define CONFIG_SYS_MALLOC_LEN           (128 << 10) /* 128 kB for malloc() */
 258 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)   /* Initial map for Linux */
 259
 260 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 261 #define CONFIG_SYS_RAMBOOT              1
 262 #endif
 263
 264 /*
 265  * Ethernet configuration
 266  */
 267 #define CONFIG_MPC5xxx_FEC
 268 #define CONFIG_MPC5xxx_FEC_MII100
 269 #define CONFIG_PHY_ADDR                 0x00
 270 #define CONFIG_RESET_PHY_R
 271
 272 /*
 273  * GPIO configuration
 274  */
 275 #define CONFIG_SYS_GPIO_DATADIR         0x00000064 /* PSC1_2, PSC2_1,2 output */
 276 #define CONFIG_SYS_GPIO_OPENDRAIN       0x00000000 /* No open drain */
 277 #define CONFIG_SYS_GPIO_DATAVALUE       0x00000000 /* PSC1_1 to 1, rest to 0 */
 278 #define CONFIG_SYS_GPIO_ENABLE          0x00000064 /* PSC1_2, PSC2_1,2 enable */
 279
 280 /*
 281  * Miscellaneous configurable options
 282  */
 283 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 284 #define CONFIG_CMDLINE_EDITING
 285
 286 #if defined(CONFIG_CMD_KGDB)
 287 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 288 #else
 289 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 290 #endif
 291 /* Print Buffer Size */
 292 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 293                                          sizeof(CONFIG_SYS_PROMPT) + 16)
 294 /* max number of command args */
 295 #define CONFIG_SYS_MAXARGS              16
 296 /* Boot Argument Buffer Size */
 297 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 298
 299 /* default load address */
 300 #define CONFIG_SYS_LOAD_ADDR            0x100000
 301
 302 /* decrementer freq: 1 ms ticks */
 303
 304 /*
 305  * Various low-level settings
 306  */
 307 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 308 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 309
 310 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
 311 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 312 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 313 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 314
 315 #define CONFIG_BOARD_EARLY_INIT_R
 316
 317 #define CONFIG_SYS_CS_BURST             0x00000000
 318 #define CONFIG_SYS_CS_DEADCYCLE         0x33333333
 319
 320 /*
 321  * DT support
 322  */
 323 #define OF_CPU                  "PowerPC,5200@0"
 324 #define OF_SOC                  "soc5200@f0000000"
 325 #define OF_TBCLK                (bd->bi_busfreq / 4)
 326
 327 #endif /* __O2D_CONFIG_H */