include/configs/o2dnt-common.h

   1 /*
   2  *  Common configuration options for ifm camera boards
   3  *
   4  * (C) Copyright 2005
   5  * Sebastien Cazaux, ifm electronic gmbh
   6  *
   7  * (C) Copyright 2012
   8  * DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __O2D_CONFIG_H
  14 #define __O2D_CONFIG_H
  15
  16 /*
  17  * High Level Configuration Options
  18  */
  19 #define CONFIG_MPC5200
  20
  21 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* running at 33.000000MHz */
  22
  23 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
  24 #if defined(CONFIG_CMD_KGDB)
  25 /* log base 2 of the above value */
  26 #define CONFIG_SYS_CACHELINE_SHIFT      5
  27 #endif
  28
  29 /*
  30 #define CONFIG_POST     (CONFIG_SYS_POST_MEMORY | \
  31                          CONFIG_SYS_POST_I2C)
  32 */
  33
  34 #ifdef CONFIG_POST
  35 /* preserve space for the post_word at end of on-chip SRAM */
  36 #define MPC5XXX_SRAM_POST_SIZE  (MPC5XXX_SRAM_SIZE - 4)
  37 #endif
  38
  39 /*
  40  * Serial console configuration
  41  */
  42 #define CONFIG_PSC_CONSOLE      5       /* console is on PSC5 */
  43 #define CONFIG_SYS_BAUDRATE_TABLE \
  44         { 9600, 19200, 38400, 57600, 115200, 230400 }
  45
  46 /*
  47  * PCI Mapping:
  48  * 0x40000000 - 0x4fffffff - PCI Memory
  49  * 0x50000000 - 0x50ffffff - PCI IO Space
  50  */
  51
  52 #define CONFIG_PCI_MEM_BUS      0x40000000
  53 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  54 #define CONFIG_PCI_MEM_SIZE     0x10000000
  55
  56 #define CONFIG_PCI_IO_BUS       0x50000000
  57 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  58 #define CONFIG_PCI_IO_SIZE      0x01000000
  59
  60 #define CONFIG_SYS_XLB_PIPELINING       1
  61
  62 /* Partitions */
  63
  64 #define CONFIG_TIMESTAMP        /* Print image info with timestamp */
  65
  66 #define CONFIG_SYS_ALT_MEMTEST  /* Much more complex memory test */
  67
  68 /*
  69  * Supported commands
  70  */
  71 #define CONFIG_CMD_EEPROM
  72 #ifdef CONFIG_PCI
  73 #define CONFIG_CMD_PCI
  74 #endif
  75
  76 #if (CONFIG_SYS_TEXT_BASE == 0xFC000000) || (CONFIG_SYS_TEXT_BASE == 0xFF000000)
  77 /* Boot low with 16 or 32 MB Flash */
  78 #define CONFIG_SYS_LOWBOOT      1
  79 #elif (CONFIG_SYS_TEXT_BASE != 0x00100000)
  80 #error "CONFIG_SYS_TEXT_BASE value is invalid"
  81 #endif
  82
  83
  84 #define CONFIG_PREBOOT  "run master"
  85
  86 #undef  CONFIG_BOOTARGS
  87
  88 #if !defined(CONSOLE_DEV)
  89 #define CONSOLE_DEV     "ttyPSC1"
  90 #endif
  91
  92 /*
  93  * Default environment for booting old and new kernel versions
  94  */
  95 #define CONFIG_IFM_DEFAULT_ENV_OLD                                      \
  96         "flash_self_old=run ramargs addip addmem;"                      \
  97                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  98         "flash_nfs_old=run nfsargs addip addmem;"                       \
  99                 "bootm ${kernel_addr}\0"                                \
 100         "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"                \
 101                 "run nfsargs addip addmem;"                             \
 102                 "bootm ${kernel_addr_r}\0"
 103
 104 #define CONFIG_IFM_DEFAULT_ENV_NEW                                      \
 105         "fdt_addr_r=900000\0"                                           \
 106         "fdt_file="CONFIG_BOARD_NAME"/"CONFIG_BOARD_NAME".dtb\0"        \
 107         "flash_self=run ramargs addip addtty addmisc;"                  \
 108                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 109         "flash_nfs=run nfsargs addip addtty addmisc;"                   \
 110                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 111         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
 112                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 113                 "run nfsargs addip addtty addmisc;"                     \
 114                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 115
 116 #define CONFIG_IFM_DEFAULT_ENV_SETTINGS                                 \
 117         "IOpin=0x64\0"                                                  \
 118         "addip=setenv bootargs ${bootargs} "                            \
 119                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 120                 ":${hostname}:${netdev}:off panic=1\0"                  \
 121         "addmem=setenv bootargs ${bootargs} ${memlimit}\0"              \
 122         "addmisc=sete bootargs ${bootargs} ${miscargs}\0"               \
 123         "addtty=sete bootargs ${bootargs} console="                     \
 124                 CONSOLE_DEV ",${baudrate}\0"                    \
 125         "bootfile="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0" \
 126         "kernel_addr_r=600000\0"                                        \
 127         "initrd_high=0x03e00000\0"                                      \
 128         "memlimit=mem="CONFIG_BOARD_MEM_LIMIT"M\0"                      \
 129         "memtest=mtest 0x00100000 "__stringify(CONFIG_SYS_MEMTEST_END)" 0 1\0" \
 130         "netdev=eth0\0"                                                 \
 131         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 132                 "nfsroot=${serverip}:${rootpath}\0"                     \
 133         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 134         "linuxname="CONFIG_BOARD_NAME"/uImage_"CONFIG_BOARD_NAME"_act\0"\
 135         "progLinux=tftp 200000 ${linuxname};erase ${linbot} ${lintop};" \
 136                 "cp.b ${fileaddr} ${linbot} ${filesize}\0"              \
 137         "ramname="CONFIG_BOARD_NAME"/uRamdisk_"CONFIG_BOARD_NAME"_act\0"\
 138         "progRam=tftp 200000 ${ramname};erase ${rambot} ${ramtop};"     \
 139                 "cp.b ${fileaddr} ${rambot} ${filesize}\0"              \
 140         "jffname="CONFIG_BOARD_NAME"/uJFFS2_"CONFIG_BOARD_NAME"_act\0"  \
 141         "progJff=tftp 200000 ${jffname};erase ${jffbot} ${jfftop};"     \
 142                 "cp.b ${fileaddr} ${jffbot} ${filesize}\0"              \
 143         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 144         "uboname=" CONFIG_BOARD_NAME                                    \
 145                 "/u-boot.bin_" CONFIG_BOARD_NAME "_act\0"               \
 146         "progubo=tftp 200000 ${uboname};"                               \
 147                 "protect off ${ubobot} ${ubotop};"                      \
 148                 "erase ${ubobot} ${ubotop};"                            \
 149                 "cp.b ${fileaddr} ${ubobot} ${filesize}\0"              \
 150         "unlock=yes\0"                                                  \
 151         "post=echo !!! "CONFIG_BOARD_NAME" POWER ON SELF TEST !!!;"     \
 152                 "setenv bootdelay 1;"                                   \
 153                 "crc32 "__stringify(CONFIG_SYS_TEXT_BASE)" "            \
 154                         BOARD_POST_CRC32_END";"                         \
 155                 "setenv bootcmd "CONFIG_BOARD_BOOTCMD";saveenv;reset\0"
 156
 157 #define CONFIG_BOOTCOMMAND      "run post"
 158
 159 /*
 160  * IPB Bus clocking configuration.
 161  */
 162 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 163
 164 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 165 /*
 166  * PCI Bus clocking configuration
 167  *
 168  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 169  * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 170  * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 171  */
 172 #define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2    /* define for 66MHz speed */
 173 #endif
 174
 175 /*
 176  * I2C configuration
 177  */
 178 #define CONFIG_HARD_I2C                 1       /* I2C with hardware support */
 179 #define CONFIG_SYS_I2C_MODULE           1       /* Select I2C module #1 or #2 */
 180 #define CONFIG_SYS_I2C_SPEED            100000  /* 100 kHz */
 181 #define CONFIG_SYS_I2C_SLAVE            0x7F
 182
 183 /*
 184  * EEPROM configuration:
 185  *
 186  * O2DNT board is equiped with Ramtron FRAM device FM24CL16
 187  * 16 Kib Ferroelectric Nonvolatile serial RAM memory
 188  * organized as 2048 x 8 bits and addressable as eight I2C devices
 189  * 0x50 ... 0x57 each 256 bytes in size
 190  *
 191  */
 192 #define CONFIG_SYS_I2C_FRAM
 193 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 194 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 195 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 196 /*
 197  * There is no write delay with FRAM, write operations are performed at bus
 198  * speed. Thus, no status polling or write delay is needed.
 199  */
 200
 201 /*
 202  * Flash configuration
 203  */
 204 #define CONFIG_SYS_FLASH_CFI            1
 205 #define CONFIG_FLASH_CFI_DRIVER         1
 206 #define CONFIG_FLASH_16BIT
 207 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 208 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
 209 #define CONFIG_SYS_FLASH_EMPTY_INFO
 210
 211 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 212 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 213 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Erase Timeout (in ms) */
 214 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Write Timeout (in ms) */
 215 /* Timeout for Flash Clear Lock Bits (in ms) */
 216 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    10000
 217 /* "Real" (hardware) sectors protection */
 218 #define CONFIG_SYS_FLASH_PROTECTION
 219
 220 /*
 221  * Environment settings
 222  */
 223 #define CONFIG_ENV_IS_IN_FLASH  1
 224 #define CONFIG_ENV_SIZE         0x20000
 225 #define CONFIG_ENV_SECT_SIZE    0x20000
 226 #define CONFIG_ENV_OVERWRITE    1
 227 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00040000)
 228
 229 /*
 230  * Memory map
 231  */
 232 #define CONFIG_SYS_MBAR         0xF0000000
 233 #define CONFIG_SYS_SDRAM_BASE   0x00000000
 234 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 235
 236 /* Use SRAM until RAM will be available */
 237 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 238 #ifdef CONFIG_POST
 239 /* preserve space for the post_word at end of on-chip SRAM */
 240 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 241 #else
 242 /* End of used area in DPRAM */
 243 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 244 #endif
 245
 246 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 247                                          GENERATED_GBL_DATA_SIZE)
 248 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 249
 250 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 251 #define CONFIG_SYS_MONITOR_LEN          (192 << 10) /* 192 kB for Monitor */
 252 #define CONFIG_SYS_MALLOC_LEN           (128 << 10) /* 128 kB for malloc() */
 253 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)   /* Initial map for Linux */
 254
 255 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 256 #define CONFIG_SYS_RAMBOOT              1
 257 #endif
 258
 259 /*
 260  * Ethernet configuration
 261  */
 262 #define CONFIG_MPC5xxx_FEC
 263 #define CONFIG_MPC5xxx_FEC_MII100
 264 #define CONFIG_PHY_ADDR                 0x00
 265 #define CONFIG_RESET_PHY_R
 266
 267 /*
 268  * GPIO configuration
 269  */
 270 #define CONFIG_SYS_GPIO_DATADIR         0x00000064 /* PSC1_2, PSC2_1,2 output */
 271 #define CONFIG_SYS_GPIO_OPENDRAIN       0x00000000 /* No open drain */
 272 #define CONFIG_SYS_GPIO_DATAVALUE       0x00000000 /* PSC1_1 to 1, rest to 0 */
 273 #define CONFIG_SYS_GPIO_ENABLE          0x00000064 /* PSC1_2, PSC2_1,2 enable */
 274
 275 /*
 276  * Miscellaneous configurable options
 277  */
 278 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 279 #define CONFIG_CMDLINE_EDITING
 280
 281 #if defined(CONFIG_CMD_KGDB)
 282 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 283 #else
 284 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 285 #endif
 286 /* Print Buffer Size */
 287 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 288                                          sizeof(CONFIG_SYS_PROMPT) + 16)
 289 /* max number of command args */
 290 #define CONFIG_SYS_MAXARGS              16
 291 /* Boot Argument Buffer Size */
 292 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 293
 294 /* default load address */
 295 #define CONFIG_SYS_LOAD_ADDR            0x100000
 296
 297 /* decrementer freq: 1 ms ticks */
 298
 299 /*
 300  * Various low-level settings
 301  */
 302 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 303 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 304
 305 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
 306 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 307 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 308 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 309
 310 #define CONFIG_BOARD_EARLY_INIT_R
 311
 312 #define CONFIG_SYS_CS_BURST             0x00000000
 313 #define CONFIG_SYS_CS_DEADCYCLE         0x33333333
 314
 315 /*
 316  * DT support
 317  */
 318 #define OF_CPU                  "PowerPC,5200@0"
 319 #define OF_SOC                  "soc5200@f0000000"
 320 #define OF_TBCLK                (bd->bi_busfreq / 4)
 321
 322 #endif /* __O2D_CONFIG_H */