include/configs/ocotea.h

   1 /*
   2  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   3  *
   4  * (C) Copyright 2005
   5  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /************************************************************************
  27  * 1 March 2004  Travis B. Sawyer <tsawyer@sandburst.com>
  28  * Adapted to current Das U-Boot source
  29  ***********************************************************************/
  30
  31
  32 /************************************************************************
  33  * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
  34  ***********************************************************************/
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*-----------------------------------------------------------------------
  40  * High Level Configuration Options
  41  *----------------------------------------------------------------------*/
  42 #define CONFIG_OCOTEA           1           /* Board is ebony           */
  43 #define CONFIG_440GX            1           /* Specifc GX support       */
  44 #define CONFIG_440              1           /* ... PPC440 family        */
  45 #define CONFIG_4xx              1           /* ... PPC4xx family        */
  46 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_pre_init      */
  47 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  48
  49 /*
  50  * Include common defines/options for all AMCC eval boards
  51  */
  52 #define CONFIG_HOSTNAME         ocotea
  53 #include "amcc-common.h"
  54
  55 /*-----------------------------------------------------------------------
  56  * Base addresses -- Note these are effective addresses where the
  57  * actual resources get mapped (not physical addresses)
  58  *----------------------------------------------------------------------*/
  59 #define CONFIG_SYS_FLASH_BASE       0xff800000      /* start of FLASH           */
  60 #define CONFIG_SYS_PCI_MEMBASE      0x80000000      /* mapped pci memory        */
  61 #define CONFIG_SYS_ISRAM_BASE       0xc0000000      /* internal SRAM            */
  62 #define CONFIG_SYS_PCI_BASE         0xd0000000      /* internal PCI regs        */
  63
  64 #define CONFIG_SYS_FPGA_BASE        (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
  65 #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
  66
  67 /*-----------------------------------------------------------------------
  68  * Initial RAM & stack pointer (placed in internal SRAM)
  69  *----------------------------------------------------------------------*/
  70 #define CONFIG_SYS_TEMP_STACK_OCM  1
  71 #define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
  72 #define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address        */
  73 #define CONFIG_SYS_INIT_RAM_END    0x2000           /* End of used area in RAM  */
  74 #define CONFIG_SYS_GBL_DATA_SIZE   128              /* num bytes initial data   */
  75
  76 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  77 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  78
  79 /*-----------------------------------------------------------------------
  80  * Serial Port
  81  *----------------------------------------------------------------------*/
  82 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  83 #define CONFIG_SYS_EXT_SERIAL_CLOCK     (1843200 * 6)   /* Ext clk @ 11.059 MHz */
  84
  85 /*-----------------------------------------------------------------------
  86  * Environment
  87  *----------------------------------------------------------------------*/
  88 /*
  89  * Define here the location of the environment variables (FLASH or NVRAM).
  90  * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
  91  *       supported for backward compatibility.
  92  */
  93 #if 1
  94 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  95 #else
  96 #define CONFIG_ENV_IS_IN_NVRAM  1       /* use NVRAM for environment vars       */
  97 #endif
  98
  99
 100 /*-----------------------------------------------------------------------
 101  * NVRAM/RTC
 102  *
 103  * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
 104  * The DS1743 code assumes this condition (i.e. -- it assumes the base
 105  * address for the RTC registers is:
 106  *
 107  *      CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
 108  *
 109  *----------------------------------------------------------------------*/
 110 #define CONFIG_SYS_NVRAM_SIZE       (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
 111 #define CONFIG_RTC_DS174x       1                   /* DS1743 RTC               */
 112
 113 #ifdef CONFIG_ENV_IS_IN_NVRAM
 114 #define CONFIG_ENV_SIZE         0x1000      /* Size of Environment vars */
 115 #define CONFIG_ENV_ADDR         \
 116         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
 117 #endif /* CONFIG_ENV_IS_IN_NVRAM */
 118
 119 /*-----------------------------------------------------------------------
 120  * FLASH related
 121  *----------------------------------------------------------------------*/
 122 #define CONFIG_SYS_MAX_FLASH_BANKS      3                   /* number of banks      */
 123 #define CONFIG_SYS_MAX_FLASH_SECT       64                  /* sectors per device   */
 124
 125 #undef  CONFIG_SYS_FLASH_CHECKSUM
 126 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 127 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 128
 129 #define CONFIG_SYS_FLASH_ADDR0         0x5555
 130 #define CONFIG_SYS_FLASH_ADDR1         0x2aaa
 131 #define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
 132
 133 #ifdef CONFIG_ENV_IS_IN_FLASH
 134 #define CONFIG_ENV_SECT_SIZE    0x10000         /* size of one complete sector  */
 135 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 136 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 137
 138 /* Address and size of Redundant Environment Sector     */
 139 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 140 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 141 #endif /* CONFIG_ENV_IS_IN_FLASH */
 142
 143 /*-----------------------------------------------------------------------
 144  * DDR SDRAM
 145  *----------------------------------------------------------------------*/
 146 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 147 #define SPD_EEPROM_ADDRESS {0x53,0x52}  /* SPD i2c spd addresses        */
 148 #define CONFIG_PROG_SDRAM_TLB   1       /* setup SDRAM TLB's dynamically*/
 149
 150 /*-----------------------------------------------------------------------
 151  * I2C
 152  *----------------------------------------------------------------------*/
 153 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 154
 155 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 156 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 157 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 158 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 159 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 160
 161 /*
 162  * Default environment variables
 163  */
 164 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 165         CONFIG_AMCC_DEF_ENV                                             \
 166         CONFIG_AMCC_DEF_ENV_PPC                                         \
 167         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 168         "kernel_addr=fff00000\0"                                        \
 169         "ramdisk_addr=fff10000\0"                                       \
 170         ""
 171
 172 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 173 #define CONFIG_PHY1_ADDR        2
 174 #define CONFIG_PHY2_ADDR        0x10
 175 #define CONFIG_PHY3_ADDR        0x18
 176 #define CONFIG_HAS_ETH0
 177 #define CONFIG_HAS_ETH1
 178 #define CONFIG_HAS_ETH2
 179 #define CONFIG_HAS_ETH3
 180 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 181 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 182 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 183 #define CONFIG_PHY_RESET_DELAY  1000
 184
 185 /*
 186  * Commands additional to the ones defined in amcc-common.h
 187  */
 188 #define CONFIG_CMD_DATE
 189 #define CONFIG_CMD_PCI
 190 #define CONFIG_CMD_SDRAM
 191 #define CONFIG_CMD_SNTP
 192
 193 /*-----------------------------------------------------------------------
 194  * PCI stuff
 195  *-----------------------------------------------------------------------
 196  */
 197 /* General PCI */
 198 #define CONFIG_PCI                      /* include pci support          */
 199 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 200 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 201 #define CONFIG_SYS_PCI_TARGBASE    0x80000000   /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 202
 203 /* Board-specific PCI */
 204 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 205
 206 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 207 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 208
 209 #endif  /* __CONFIG_H */