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1 /*
2 * (C) Copyright 2003-2004
3 * MPC Data Limited (http://www.mpc-data.co.uk)
4 * Dave Peverley <dpeverley at mpc-data.co.uk>
5 *
6 * Configuation settings for the TI OMAP Perseus 2 board.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11 #ifndef __CONFIG_H
12 #define __CONFIG_H
13
14 /* allow to overwrite serial and ethaddr */
15 #define CONFIG_ENV_OVERWRITE
16
17 /*
18 * High Level Configuration Options
19 * (easy to change)
20 */
21
22 #define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */
23 #define CONFIG_OMAP 1 /* in a TI OMAP core */
24 #define CONFIG_OMAP730 1 /* which is in a 730 */
25 #define CONFIG_P2_OMAP730 1 /* a Perseus 2 Board */
26
27 /*
28 * Input clock of PLL
29 * The OMAP730 Perseus 2 has 13MHz input clock
30 */
31
32 #define CONFIG_SYS_CLK_FREQ 13000000
33
34 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
35 #define CONFIG_SETUP_MEMORY_TAGS 1
36
37 /*
38 * Size of malloc() pool
39 */
40
41 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
42
43 /*
44 * Hardware drivers
45 */
46
47 #define CONFIG_LAN91C96
48 #define CONFIG_LAN91C96_BASE 0x04000300
49 #define CONFIG_LAN91C96_EXT_PHY
50
51 /*
52 * NS16550 Configuration
53 */
54
55 #define CONFIG_SYS_NS16550
56 #define CONFIG_SYS_NS16550_SERIAL
57 #define CONFIG_SYS_NS16550_REG_SIZE (1)
58 #define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */
59 #define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart
60 * on perseus */
61
62 /*
63 * select serial console configuration
64 */
65
66 #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP730 Perseus 2 */
67
68 #define CONFIG_CONS_INDEX 1
69 #define CONFIG_BAUDRATE 115200
70
71 /*
72 * Command line configuration.
73 */
74 #include <config_cmd_default.h>
75
76 #define CONFIG_CMD_DHCP
77
78
79 /*
80 * BOOTP options
81 */
82 #define CONFIG_BOOTP_SUBNETMASK
83 #define CONFIG_BOOTP_GATEWAY
84 #define CONFIG_BOOTP_HOSTNAME
85 #define CONFIG_BOOTP_BOOTPATH
86
87
88 #include <configs/omap730.h>
89 #include <configs/h2_p2_dbg_board.h>
90
91 #define CONFIG_BOOTDELAY 3
92 #define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw ip=bootp"
93
94 #define CONFIG_LOADADDR 0x10000000
95
96 #define CONFIG_ETHADDR
97 #define CONFIG_NETMASK 255.255.255.0
98 #define CONFIG_IPADDR 192.168.0.23
99 #define CONFIG_SERVERIP 192.150.0.100
100 #define CONFIG_BOOTFILE "uImage" /* File to load */
101
102 #if defined(CONFIG_CMD_KGDB)
103 #define CONFIG_KGDB_BAUDRATE 115200 /* Speed to run kgdb serial port */
104 #define CONFIG_KGDB_SER_INDEX 1 /* Which serial port to use */
105 #endif
106
107 /*
108 * Miscellaneous configurable options
109 */
110
111 #define CONFIG_SYS_LONGHELP /* undef to save memory */
112 #define CONFIG_SYS_PROMPT "OMAP730 P2 # " /* Monitor Command Prompt */
113 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
114 /* Print Buffer Size */
115 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
116 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
117 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
118
119 #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */
120 #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */
121
122 #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */
123
124 /* The OMAP730 has 3 general purpose MPU timers, they can be driven by
125 * the RefClk (12Mhz) or by DPLL1. This time is further subdivided by a
126 * local divisor.
127 */
128 #define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */
129 #define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */
130 #define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV))
131
132 /*-----------------------------------------------------------------------
133 * Physical Memory Map
134 */
135
136 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
137 #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
138 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
139
140 #if defined(CONFIG_CS0_BOOT)
141 #define PHYS_FLASH_1 0x0C000000
142 #elif defined(CONFIG_CS3_BOOT)
143 #define PHYS_FLASH_1 0x00000000
144 #else
145 #error Unknown Boot Chip-Select number
146 #endif
147
148 #define PHYS_SRAM 0x20000000
149
150 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
151
152 /*-----------------------------------------------------------------------
153 * FLASH and environment organization
154 */
155
156 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
157 #define PHYS_FLASH_SIZE 0x02000000 /* 32MB */
158 #define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */
159 /* addr of environment */
160 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000)
161
162 /* timeout values are in ticks */
163 #define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
164 #define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */
165
166 #define CONFIG_ENV_IS_IN_FLASH 1
167 #define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */
168 #define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */
169
170 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
171 #define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM
172
173 #endif /* ! __CONFIG_H */